2003 |
10 | EE | Bharat Krishna,
C. Y. Roger Chen,
Naresh Sehgal:
A novel ultra-fast heuristic for VLSI CAD steiner trees.
ACM Great Lakes Symposium on VLSI 2003: 192-197 |
9 | EE | Bill Halpin,
Naresh Sehgal,
C. Y. Roger Chen:
Detailed Placement with Net Length Constraints.
IWSOC 2003: 22-27 |
2001 |
8 | EE | Bill Halpin,
C. Y. Roger Chen,
Naresh Sehgal:
Timing Driven Placement using Physical Net Constraints.
DAC 2001: 780-783 |
2000 |
7 | EE | Bill Halpin,
C. Y. Roger Chen,
Naresh Sehgal:
A sensitivity based placer for standard cells.
ACM Great Lakes Symposium on VLSI 2000: 193-196 |
6 | EE | Bharat Krishna,
C. Y. Roger Chen,
Naresh Sehgal:
A novel technique for sea of gates global routing.
ACM Great Lakes Symposium on VLSI 2000: 71-74 |
1999 |
5 | EE | Bulent Basaran,
Kiran Ganesh,
Raymond Y. K. Lau,
Artour Levin,
Miles McCoo,
Srinivasan Rangarajan,
Naresh Sehgal:
GeneSys: A Leaf-Cell Layout Synthesis System for GHz VLSI Designs.
VLSI Design 1999: 448-452 |
4 | EE | Amit Chowdhary,
Sudhakar Kale,
Phani K. Saripella,
Naresh Sehgal,
Rajesh K. Gupta:
Extraction of functional regularity in datapath circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 18(9): 1279-1296 (1999) |
1998 |
3 | EE | Amit Chowdhary,
Sudhakar Kale,
Phani K. Saripella,
Naresh Sehgal,
Rajesh K. Gupta:
A general approach for regularity extraction in datapath circuits.
ICCAD 1998: 332-339 |
2 | | Bharat Krishna,
C. Y. Roger Chen,
Naresh Sehgal:
Technique for Planning of Terminal Locations of Leaf Cells in Cell-Based Design with Routing Considerations.
VLSI Design 1998: 53-58 |
1994 |
1 | EE | Naresh Sehgal,
C. Y. Roger Chen,
John M. Acken:
An object-oriented cell library manager.
ICCAD 1994: 750-753 |