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Ireneusz Janiszewski

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2004
3EEIreneusz Janiszewski, Hermann Meuth, Bernhard Hoppe: FPGA-Efficient Hybrid LUT/CORDIC Architecture. FPL 2004: 933-937
2002
2 Ireneusz Janiszewski, Bernhard Hoppe, Hermann Meuth: Modelling and Simulation in the Design Flow for Numerically Controlled Oscillators. ESM 2002: 625-629
2001
1EEIreneusz Janiszewski, Bernhard Hoppe, Hermann Meuth: VHDL-Based Design and Design Methodology for Reusable High Performance Direct Digital Frequency Synthesizers. DAC 2001: 573-578

Coauthor Index

1Bernhard Hoppe [1] [2] [3]
2Hermann Meuth [1] [2] [3]

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)