| 2005 |
|---|
| 6 | | Amit Gupta,
Charles Selvidge:
Acyclic modeling of combinational loops.
ICCAD 2005: 343-347 |
| 5 | EE | Soha Hassoun,
Murali Kudlugi,
Duaine Pryor,
Charles Selvidge:
A transaction-based unified architecture for simulation and emulation.
IEEE Trans. VLSI Syst. 13(2): 278-287 (2005) |
| 2001 |
|---|
| 4 | EE | Murali Kudlugi,
Soha Hassoun,
Charles Selvidge,
Duaine Pryor:
A Transaction-Based Unified Simulation/Emulation Architecture for Functional Verification.
DAC 2001: 623-628 |
| 3 | EE | Murali Kudlugi,
Charles Selvidge,
Russell Tessier:
Static Scheduling of Multiple Asynchronous Domains For Functional Verification.
DAC 2001: 647-652 |
| 2 | EE | Murali Kudlugi,
Charles Selvidge,
Russell Tessier:
Static Scheduling of Multi-Domain Memories For Functional Verification.
ICCAD 2001: 2-9 |
| 1995 |
|---|
| 1 | EE | Charles Selvidge,
Anant Agarwal,
Matthew Dahl,
Jonathan Babb:
TIERS: Topology Independent Pipelined Routing and Scheduling for VirtualWire Compilation.
FPGA 1995: 25-31 |
