2008 |
18 | EE | Hazem Moussa,
Amer Baghdadi,
Michel Jézéquel:
Binary de Bruijn on-chip network for a flexible multiprocessor LDPC decoder.
DAC 2008: 429-434 |
17 | EE | Hazem Moussa,
Amer Baghdadi,
Michel Jézéquel:
Binary de Bruijn interconnection network for a flexible LDPC/turbo decoder.
ISCAS 2008: 97-100 |
2007 |
16 | EE | Hazem Moussa,
Olivier Muller,
Amer Baghdadi,
Michel Jézéquel:
Butterfly and benes-based on-chip communication networks for multiprocessor turbo decoding.
DATE 2007: 654-659 |
2006 |
15 | EE | Olivier Muller,
Amer Baghdadi,
Michel Jézéquel:
ASIP-based multiprocessor SoC design for simple and double binary turbo decoding.
DATE 2006: 1330-1335 |
14 | EE | Olivier Muller,
Amer Baghdadi,
Michel Jézéquel:
On the Parallelism of Convolutional Turbo Decoding and Interleaving Interference.
GLOBECOM 2006 |
2005 |
13 | EE | Nacer-Eddine Zergainoh,
Amer Baghdadi,
Ahmed Amine Jerraya:
Hardware/software codesign of on-chip communication architecture for application-specific multiprocessor system-on-chip.
IJES 1(1/2): 112-124 (2005) |
2004 |
12 | EE | Sang-Il Han,
Amer Baghdadi,
Marius Bonaciu,
Soo-Ik Chae,
Ahmed Amine Jerraya:
An efficient scalable and flexible data transfer architecture for multiprocessor SoC with massive distributed memory.
DAC 2004: 250-255 |
11 | EE | Ferid Gharsalli,
Amer Baghdadi,
Marius Bonaciu,
Giedrius Majauskas,
Wander O. Cesário,
Ahmed Amine Jerraya:
An Efficient Architecture for the Implementation of Message Passing Programming Model on Massive Multiprocessor.
IEEE International Workshop on Rapid System Prototyping 2004: 80-87 |
2003 |
10 | EE | Arif Sasongko,
Amer Baghdadi,
Frédéric Rousseau,
Ahmed Amine Jerraya:
Embedded Application Prototyping on a Communication-Restricted Reconfigurable.
IEEE International Workshop on Rapid System Prototyping 2003: 33-39 |
2002 |
9 | EE | Wander O. Cesário,
Amer Baghdadi,
Lovic Gauthier,
Damien Lyonnard,
Gabriela Nicolescu,
Yanick Paviot,
Sungjoo Yoo,
Ahmed Amine Jerraya,
Mario Diaz-Nava:
Component-based design approach for multicore SoCs.
DAC 2002: 789-794 |
8 | EE | Amer Baghdadi,
Nacer-Eddine Zergainoh,
Wander O. Cesário,
Ahmed Amine Jerraya:
Combining a Performance Estimation Methodology with a Hardware/Software Codesign Flow Supporting Multiprocessor Systems.
IEEE Trans. Software Eng. 28(9): 822-831 (2002) |
7 | EE | Amer Baghdadi,
Nacer-Eddine Zergainoh,
Wander O. Cesário,
Ahmed Amine Jerraya:
Exploration de l'espace des solutions architecturales dans le codesign.
Technique et Science Informatiques 21(1): 9-35 (2002) |
2001 |
6 | EE | Sungjoo Yoo,
Gabriela Nicolescu,
Damien Lyonnard,
Amer Baghdadi,
Ahmed Amine Jerraya:
A generic wrapper architecture for multi-processor SoC cosimulation and design.
CODES 2001: 195-200 |
5 | EE | Damien Lyonnard,
Sungjoo Yoo,
Amer Baghdadi,
Ahmed Amine Jerraya:
Automatic Generation of Application-Specific Architectures for Heterogeneous Multiprocessor System-on-Chip.
DAC 2001: 518-523 |
4 | EE | Amer Baghdadi,
Damien Lyonnard,
Nacer-Eddine Zergainoh,
Ahmed Amine Jerraya:
An efficient architecture model for systematic design of application-specific multiprocessor SoC.
DATE 2001: 55-63 |
2000 |
3 | | Amer Baghdadi,
Nacer-Eddine Zergainoh,
Damien Lyonnard,
Ahmed Amine Jerraya:
Generic Architecture Platform for Multiprocessor System-On-Chip Design.
DIPES 2000: 53-64 |
2 | | Nacer-Eddine Zergainoh,
Amer Baghdadi,
Ludovic Tambour,
Damien Lyonnard,
Lovic Gauthier,
Ahmed Amine Jerraya:
Framework for System Design, Validation and Fast Prototyping of Multiprocessor System-On-Chip.
DIPES 2000: 99-110 |
1 | EE | Amer Baghdadi,
Nacer-Eddine Zergainoh,
Wander O. Cesário,
T. Roudier,
Ahmed Amine Jerraya:
Design Space Exploration for Hardware/Software Codesign of Multiprocessor Systems.
IEEE International Workshop on Rapid System Prototyping 2000: 8-13 |