| 2006 |
|---|
| 9 | EE | Jason Baumgartner,
Hari Mony,
Viresh Paruthi,
Robert Kanzelman,
Geert Janssen:
Scalable Sequential Equivalence Checking across Arbitrary Design Transformations .
ICCD 2006 |
| 2005 |
|---|
| 8 | EE | Viresh Paruthi,
Christian Jacobi,
Kai Weber:
Efficient Symbolic Simulation via Dynamic Scheduling, Don't Caring, and Case Splitting.
CHARME 2005: 114-128 |
| 7 | EE | Hari Mony,
Jason Baumgartner,
Viresh Paruthi,
Robert Kanzelman:
Exploiting suspected redundancy without proving it.
DAC 2005: 463-466 |
| 6 | EE | Christian Jacobi,
Kai Weber,
Viresh Paruthi,
Jason Baumgartner:
Automatic Formal Verification of Fused-Multiply-Add FPUs.
DATE 2005: 1298-1303 |
| 2004 |
|---|
| 5 | EE | Hari Mony,
Jason Baumgartner,
Viresh Paruthi,
Robert Kanzelman,
Andreas Kuehlmann:
Scalable Automated Verification via Expert-System Guided Transformations.
FMCAD 2004: 159-173 |
| 2002 |
|---|
| 4 | EE | John M. Ludden,
Wolfgang Roesner,
Gerry M. Heiling,
John R. Reysa,
Jonathan R. Jackson,
Bing-Lun Chu,
Michael L. Behm,
Jason Baumgartner,
Richard D. Peterson,
Jamee Abdulhafiz,
William E. Bucy,
John H. Klaus,
Danny J. Klema,
Tien N. Le,
F. Danette Lewis,
Philip E. Milling,
Lawrence A. McConville,
Bradley S. Nelson,
Viresh Paruthi,
Travis W. Pouarz,
Audre D. Romonosky,
Jeff Stuecheli,
Kent D. Thompson,
Dave W. Victor,
Bruce Wile:
Functional verification of the POWER4 microprocessor and POWER4 multiprocessor system.
IBM Journal of Research and Development 46(1): 53-76 (2002) |
| 3 | EE | Andreas Kuehlmann,
Viresh Paruthi,
Florian Krohm,
Malay K. Ganai:
Robust Boolean reasoning for equivalence checking and functional property verification.
IEEE Trans. on CAD of Integrated Circuits and Systems 21(12): 1377-1394 (2002) |
| 2001 |
|---|
| 2 | EE | Andreas Kuehlmann,
Malay K. Ganai,
Viresh Paruthi:
Circuit-based Boolean Reasoning.
DAC 2001: 232-237 |
| 2000 |
|---|
| 1 | EE | Viresh Paruthi,
Andreas Kuehlmann:
Equivalence Checking Combining a Structural SAT-Solver, BDDs, and Simulation.
ICCD 2000: 459-464 |
