| 2007 |
|---|
| 7 | EE | Christian Jakob,
A. Th. Schwarzbacher,
Bernhard Hoppe,
R. Peters:
A FPGA Optimised Digital Real-Time Mutichannel Correlator Architecture.
DSD 2007: 35-42 |
| 2004 |
|---|
| 6 | EE | Ireneusz Janiszewski,
Hermann Meuth,
Bernhard Hoppe:
FPGA-Efficient Hybrid LUT/CORDIC Architecture.
FPL 2004: 933-937 |
| 2002 |
|---|
| 5 | | Ireneusz Janiszewski,
Bernhard Hoppe,
Hermann Meuth:
Modelling and Simulation in the Design Flow for Numerically Controlled Oscillators.
ESM 2002: 625-629 |
| 2001 |
|---|
| 4 | EE | Ireneusz Janiszewski,
Bernhard Hoppe,
Hermann Meuth:
VHDL-Based Design and Design Methodology for Reusable High Performance Direct Digital Frequency Synthesizers.
DAC 2001: 573-578 |
| 1999 |
|---|
| 3 | EE | M. Engels,
Bernhard Hoppe,
Hermann Meuth,
R. Peters:
A single chip 200 MHz digital correlation system for laser spectroscopy with 512 correlation channels.
ISCAS (5) 1999: 160-163 |
| 1990 |
|---|
| 2 | EE | Veronika Eisele,
Bernhard Hoppe,
Oliver Kiehl:
Transmission gate delay models for circuit optimization.
EURO-DAC 1990: 558-562 |
| 1 | EE | Bernhard Hoppe,
Gerd Neuendorf,
Doris Schmitt-Landsiedel,
J. Will Specks:
Optimization of high-speed CMOS logic circuits with analytical models for signal delay, chip area, and dynamic power dissipation.
IEEE Trans. on CAD of Integrated Circuits and Systems 9(3): 236-247 (1990) |
