| 2001 |
|---|
| 7 | EE | Jagesh V. Sanghavi,
Albert Wang:
Estimation of Speed, Area, and Power of Parameterizable, Soft IP.
DAC 2001: 31-34 |
| 1996 |
|---|
| 6 | EE | Jagesh V. Sanghavi,
Rajeev K. Ranjan,
Robert K. Brayton,
Alberto L. Sangiovanni-Vincentelli:
High Performance BDD Package By Exploiting Memory Hiercharchy.
DAC 1996: 635-640 |
| 5 | EE | Rajeev K. Ranjan,
Jagesh V. Sanghavi,
Robert K. Brayton,
Alberto L. Sangiovanni-Vincentelli:
Binary decision diagrams on network of workstation.
ICCD 1996: 358-364 |
| 1994 |
|---|
| 4 | EE | Eric Tomacruz,
Jagesh V. Sanghavi,
Alberto L. Sangiovanni-Vincentelli:
A parallel iterative linear solver for solving irregular grid semiconductor device matrices.
SC 1994: 24-33 |
| 1993 |
|---|
| 3 | EE | Patrick C. McGeer,
Jagesh V. Sanghavi,
Robert K. Brayton,
Alberto L. Sangiovanni-Vincentelli:
Espresso-Signature: A New Exact Minimizer for Logic Functions.
DAC 1993: 618-624 |
| 2 | | Patrick C. McGeer,
Jagesh V. Sanghavi,
Robert K. Brayton,
Alberto L. Sangiovanni-Vincentelli:
Minimization of Logic Functions Using Essential Signature Sets.
VLSI Design 1993: 323-328 |
| 1 | EE | Patrick C. McGeer,
Jagesh V. Sanghavi,
Robert K. Brayton,
Alberto L. Sangiovanni-Vincentelli:
ESPRESSO-SIGNATURE: a new exact minimizer for logic functions.
IEEE Trans. VLSI Syst. 1(4): 432-440 (1993) |
