2006 |
22 | EE | Daniel Geist,
Mark Ginzburg,
Yoad Lustig,
Ishai Rabinovitz,
Ohad Shacham,
Rachel Tzoref:
Supporting SAT based BMC on Finite Path Models.
Electr. Notes Theor. Comput. Sci. 144(1): 67-77 (2006) |
2005 |
21 | EE | Anat Dahan,
Daniel Geist,
Leonid Gluhovsky,
Dmitry Pidan,
Gil Shapir,
Yaron Wolfsthal,
Lyes Benalycherif,
Romain Kamdem,
Younes Lahbib:
Combining System Level Modeling with Assertion Based Verification.
ISQED 2005: 310-315 |
20 | EE | Baruch Schieber,
Daniel Geist,
Ayal Zaks:
Computing the minimum DNF representation of Boolean functions defined by intervals.
Discrete Applied Mathematics 149(1-3): 154-173 (2005) |
2003 |
19 | | Daniel Geist,
Enrico Tronci:
Correct Hardware Design and Verification Methods, 12th IFIP WG 10.5 Advanced Research Working Conference, CHARME 2003, L'Aquila, Italy, October 21-24, 2003, Proceedings
Springer 2003 |
18 | EE | Daniel Geist:
The PSL/Sugar Specification Language A Language for all Seasons.
CHARME 2003: 3 |
17 | EE | Shoham Ben-David,
Cindy Eisner,
Daniel Geist,
Yaron Wolfsthal:
Model Checking at IBM.
Formal Methods in System Design 22(2): 101-108 (2003) |
2002 |
16 | EE | Sharon Barner,
Daniel Geist,
Anna Gringauze:
Symbolic Localization Reduction with Reconstruction Layering and Backtracking.
CAV 2002: 65-77 |
15 | | Tamir Heyman,
Daniel Geist,
Orna Grumberg,
Assaf Schuster:
A Scalable Parallel Algorithm for Reachability Analysis of Very Large Circuits.
Formal Methods in System Design 21(3): 317-338 (2002) |
2001 |
14 | EE | Julia Dushina,
Mike Benjamin,
Daniel Geist:
Semi-Formal Test Generation with Genevieve.
DAC 2001: 617-622 |
13 | EE | Julia Dushina,
Mike Benjamin,
Daniel Geist:
Semi-Formal Test Generation for a Block of Industrial DSP.
VTS 2001: 131-137 |
12 | | Yael Abarbanel-Vinov,
Neta Aizenbud-Reshef,
Ilan Beer,
Cindy Eisner,
Daniel Geist,
Tamir Heyman,
Iris Reuveni,
Eran Rippel,
Irit Shitsevalov,
Yaron Wolfsthal,
Tali Yatzkar-Haham:
On the Effective Deployment of Functional Formal Verification.
Formal Methods in System Design 19(1): 35-44 (2001) |
2000 |
11 | | Tamir Heyman,
Daniel Geist,
Orna Grumberg,
Assaf Schuster:
Achieving Scalability in Parallel Reachability Analysis of Very Large Circuits.
CAV 2000: 20-35 |
1999 |
10 | EE | Sagi Katz,
Orna Grumberg,
Daniel Geist:
"Have I written enough Properties?" - A Method of Comparison between Specification and Implementation.
CHARME 1999: 280-297 |
9 | EE | Daniel Geist,
Giora Biran,
Tamarah Arons,
Michael Slavkin,
Yvgeny Nustov,
Monica Farkas,
Karen Holtz,
Andy Long,
Dave King,
Steve Barret:
A Methodology for the Verification of a ``System on Chip''.
DAC 1999: 574-579 |
8 | EE | Mike Benjamin,
Daniel Geist,
Alan Hartman,
Gérard Mas,
Ralph Smeets,
Yaron Wolfsthal:
A Study in Coverage-Driven Test Generation.
DAC 1999: 970-975 |
1997 |
7 | | Ilan Beer,
Shoham Ben-David,
Cindy Eisner,
Daniel Geist,
Leonid Gluhovsky,
Tamir Heyman,
Avner Landver,
P. Paanah,
Yoav Rodeh,
G. Ronin,
Yaron Wolfsthal:
RuleBase: Model Checking at IBM.
CAV 1997: 480-483 |
1996 |
6 | | Daniel Geist,
Monica Farkas,
Avner Landver,
Yossi Lichtenstein,
Shmuel Ur,
Yaron Wolfsthal:
Coverage-Directed Test Generation Using Symbolic Techniques.
FMCAD 1996: 143-158 |
1995 |
5 | EE | Ashok K. Chandra,
Vijay S. Iyengar,
D. Jameson,
R. V. Jawalekar,
Indira Nair,
Barry K. Rosen,
Michael P. Mullen,
J. Yoon,
R. Armoni,
Daniel Geist,
Yaron Wolfsthal:
AVPGEN-A test generator for architecture verification.
IEEE Trans. VLSI Syst. 3(2): 188-200 (1995) |
1994 |
4 | | Ilan Beer,
Shoham Ben-David,
Daniel Geist,
Raanan Gewirtzman,
Michael Yoeli:
Methodology and System for Practical Formal Verification of Reactive Hardware.
CAV 1994: 182-193 |
3 | | Daniel Geist,
Ilan Beer:
Efficient Model Checking by Automated Ordering of Transition Relation Partitions.
CAV 1994: 299-310 |
1992 |
2 | EE | Daniel Geist,
Ervin Y. Rodin:
Adjacency of the 0-1 knapsack problem.
Computers & OR 19(8): 797-800 (1992) |
1989 |
1 | EE | Daniel Geist,
Michael W. Vannier:
PC-based 3-D reconstruction of medical images.
Computers & Graphics 13(2): 135-143 (1989) |