| |
| 2001 | ||
|---|---|---|
| 5 | EE | Clayton B. McDonald, Randal E. Bryant: Computing Logic-Stage Delays Using Circuit Simulation and Symbolic Elmore Analysis. DAC 2001: 283-288 |
| 4 | EE | Clayton B. McDonald, Randal E. Bryant: A Symbolic Simulation-Based Methodology for Generating Black-Box Timing Models of Custom Macrocells. ICCAD 2001: 501-506 |
| 3 | EE | Clayton B. McDonald, Randal E. Bryant: CMOS circuit verification with symbolic switch-level timingsimulation. IEEE Trans. on CAD of Integrated Circuits and Systems 20(3): 458-474 (2001) |
| 2000 | ||
| 2 | EE | Clayton B. McDonald, Randal E. Bryant: Symbolic timing simulation using cluster scheduling. DAC 2000: 254-259 |
| 1999 | ||
| 1 | EE | Clayton B. McDonald, Randal E. Bryant: Symbolic functional and timing verification of transistor-level circuits. ICCAD 1999: 526-530 |
| 1 | Randal E. Bryant | [1] [2] [3] [4] [5] |