| 2005 |
|---|
| 7 | EE | Aniket,
Ravishankar Arunachalam:
Novel Algorithm for Testing Crosstalk Induced Delay Faults in VLSI Circuits.
VLSI Design 2005: 479-484 |
| 2004 |
|---|
| 6 | EE | Siddharth Garg,
Siddharth Tata,
Ravishankar Arunachalam:
Static Transition Probability Analysis Under Uncertainty.
ICCD 2004: 380-386 |
| 2003 |
|---|
| 5 | EE | Ravishankar Arunachalam,
Emrah Acar,
Sani R. Nassif:
Optimal shielding/spacing metrics for low power design.
ISVLSI 2003: 167-172 |
| 2001 |
|---|
| 4 | EE | Ravishankar Arunachalam,
Ronald D. Blanton,
Lawrence T. Pileggi:
False Coupling Interactions in Static Timing Analysis.
DAC 2001: 726-731 |
| 2000 |
|---|
| 3 | EE | Ravishankar Arunachalam,
Karthik Rajagopal,
Lawrence T. Pileggi:
TACO: timing analysis with coupling.
DAC 2000: 266-269 |
| 1998 |
|---|
| 2 | EE | Paul D. Gross,
Ravishankar Arunachalam,
Karthik Rajagopal,
Lawrence T. Pileggi:
Determination of worst-case aggressor alignment for delay calculation.
ICCAD 1998: 212-219 |
| 1997 |
|---|
| 1 | | Ravishankar Arunachalam,
Florentin Dartu,
Lawrence T. Pileggi:
CMOS Gate Delay Models for General RLC Loading.
ICCD 1997: 224-229 |
