Phillip Restle

Phillip J. Restle

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11EERex Berridge, Robert M. Averill III, Arnold E. Barish, Michael A. Bowen, Peter J. Camporese, Jack DiLullo, Peter E. Dudley, Joachim Keinert, David W. Lewis, Robert D. Morel, Thomas Rosser, Nicole S. Schwartz, Philip Shephard, Howard H. Smith, Dave Thomas, Phillip J. Restle, John R. Ripley, Stephen L. Runyon, Patrick M. Williams: IBM POWER6 microprocessor physical design and design methodology. IBM Journal of Research and Development 51(6): 685-714 (2007)
10EEGerald G. Lopez, Giovanni Fiorenza, Thomas J. Bucelot, Phillip Restle, Mary Yvonne Lanzerotti: Characterization of the impact of interconnect design on the capacitive load driven by a global clock distribution. ACM Great Lakes Symposium on VLSI 2005: 38-43
9 Phillip Restle, Kenneth L. Shepard: New Prospects for Clocking Synchronous and Quasi-Asynchronous Systems. ASYNC 2005
8EEJoachim G. Clabes, Joshua Friedrich, Mark Sweet, Jack DiLullo, Sam Chu, Donald W. Plass, James Dawson, Paul Muench, Larry Powell, Michael S. Floyd, Balaram Sinharoy, Mike Lee, Michael Goulet, James Wagoner, Nicole S. Schwartz, Stephen L. Runyon, Gary Gorman, Phillip Restle, Ronald N. Kalla, Joseph McGill, Steve Dodson: Design and implementation of the POWER5 microprocessor. DAC 2004: 670-672
7EESteven C. Chan, Kenneth L. Shepard, Phillip Restle: Design of Resonant Global Clock Distributions. ICCD 2003: 248-253
6EEJames D. Warnock, John M. Keaty, John G. Petrovick, Joachim G. Clabes, Charles J. Kircher, Byron Krauter, Phillip Restle, Brian A. Zoric, Carl J. Anderson: The circuit and physical design of the POWER4 microprocessor. IBM Journal of Research and Development 46(1): 27-52 (2002)
5EEPhillip Restle: Technical Visualizations in VLSI Design. DAC 2001: 494-499
4EEPhillip Restle, Albert E. Ruehli, Steven G. Walker: Multi-GHz interconnect effects in microprocessors. ISPD 2001: 93-97
3EEPhillip Restle, Albert E. Ruehli, Steven G. Walker, George Papadopoulos: Full-wave PEEC time-domain method for the modeling of on-chipinterconnects. IEEE Trans. on CAD of Integrated Circuits and Systems 20(7): 877-886 (2001)
2EEPhillip Restle, Albert E. Ruehli, Steven G. Walker: Dealing with Inductance in High-Speed Chip Design. DAC 1999: 904-909
1EEPhillip Restle, Joel R. Phillips, Ibrahim M. Elfadel: Interconnect in high speed designs: problems, methodologies and tools. ICCAD 1998: 4

Coauthor Index

1Carl J. Anderson [6]
2Robert M. Averill III [11]
3Arnold E. Barish [11]
4Rex Berridge [11]
5Michael A. Bowen [11]
6Thomas J. Bucelot [10]
7Peter J. Camporese [11]
8Steven C. Chan [7]
9Sam Chu [8]
10Joachim G. Clabes [6] [8]
11James Dawson [8]
12Jack DiLullo [8] [11]
13Steve Dodson [8]
14Peter E. Dudley [11]
15Ibrahim M. Elfadel [1]
16Giovanni Fiorenza [10]
17Michael S. Floyd [8]
18Joshua Friedrich [8]
19Gary Gorman [8]
20Michael Goulet [8]
21Ronald N. Kalla [8]
22John M. Keaty [6]
23Joachim Keinert [11]
24Charles J. Kircher [6]
25Byron Krauter [6]
26Mary Yvonne Lanzerotti [10]
27Mike Lee [8]
28David W. Lewis [11]
29Gerald G. Lopez [10]
30Joseph McGill [8]
31Robert D. Morel [11]
32Paul Muench [8]
33George Papadopoulos [3]
34John G. Petrovick [6]
35Joel R. Phillips [1]
36Donald W. Plass [8]
37Larry Powell [8]
38John R. Ripley [11]
39Thomas Rosser [11]
40Albert E. Ruehli [2] [3] [4]
41Stephen L. Runyon [8] [11]
42Nicole S. Schwartz [8] [11]
43Kenneth L. Shepard [7] [9]
44Philip Shephard [11]
45Balaram Sinharoy [8]
46Howard H. Smith [11]
47Mark Sweet [8]
48Dave Thomas [11]
49James Wagoner [8]
50Steven G. Walker [2] [3] [4]
51James D. Warnock [6]
52Patrick M. Williams [11]
53Brian A. Zoric [6]

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Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)