Sying-Jyan Wang

2008
24	EE	Sying-Jyan Wang, Shih-Cheng Chen, Katherine Shu-Min Li: Design and analysis of skewed-distribution scan chain partition for improved test data compression. ISCAS 2008: 2641-2644
23	EE	Sying-Jyan Wang, Kuo-Lin Peng, Kuang-Cyun Hsiao, Katherine Shu-Min Li: Layout-aware scan chain reorder for launch-off-shift transition test coverage. ACM Trans. Design Autom. Electr. Syst. 13(4): (2008)
2007
22	EE	Sying-Jyan Wang, Tung-Hua Yeh: High-level test synthesis for delay fault testability. DATE 2007: 45-50
21	EE	Sying-Jyan Wang, Yan-Ting Chen, Katherine Shu-Min Li: Low Capture Power Test Generation for Launch-off-Capture Transition Test Based on Don't-Care Filling. ISCAS 2007: 3683-3686
20	EE	Po-Chang Tsai, Sying-Jyan Wang, Ching-Hung Lin, Tung-Hua Yeh: Test Data Compression for Minimum Test Application Time. J. Inf. Sci. Eng. 23(6): 1901-1909 (2007)
2005
19	EE	Yu-Hsuan Fu, Sying-Jyan Wang: Test Data Compression with Partial LFSR-Reseeding. Asian Test Symposium 2005: 343-347
18	EE	Ming-Chen Wen, Sying-Jyan Wang, Yen-Nan Lin: Low power parallel multiplier with column bypassing. ISCAS (2) 2005: 1638-1641
2004
17	EE	Nan-Cheng Lai, Sying-Jyan Wang, Yu-Hsuan Fu: Low Power BIST with Smoother and Scan-Chain Reorder . Asian Test Symposium 2004: 40-45
2002
16	EE	Nan-Cheng Li, Sying-Jyan Wang: A Reseeding Technique for LFSR-Based BIST Applications. Asian Test Symposium 2002: 200-205
15	EE	Yu-Lung Hsu, Sying-Jyan Wang: Retiming-based logic synthesis for low-power. ISLPED 2002: 275-278
2001
14	EE	Sying-Jyan Wang, Sheng-Nan Chiou: Generating Efficient Tests for Continuous Scan. DAC 2001: 162-165
13	EE	Sying-Jyan Wang: Distributed Diagnosis in Multistage Interconnection Networks. J. Parallel Distrib. Comput. 61(2): 254-264 (2001)
2000
12	EE	Sying-Jyan Wang, Chen-Jung Wei: Efficient built-in self-test algorithm for memory. Asian Test Symposium 2000: 66-
11	EE	Sying-Jyan Wang, Chia-Chun Lien: Testability Improvement by Branch Point Control for Conditional Staements With Multiple Branches. J. Inf. Sci. Eng. 16(5): 719-731 (2000)
1998
10	EE	Sying-Jyan Wang, Chao-Neng Huang: Testing and Diagnosis of Interconnect Structures in FPGAs. Asian Test Symposium 1998: 283-
1997
9	EE	Sying-Jyan Wang, Tsi-Ming Tsai: Test and diagnosis of fault logic blocks in FPGAs. ICCAD 1997: 722-727
8	EE	Sying-Jyan Wang: Distributed Routing in a Fault-Tolerant Multistage Interconnection Network. Inf. Process. Lett. 63(4): 205-210 (1997)
1996
7	EE	Po-Ching Hsu, Sying-Jyan Wang: Testing And Diagnosis Of Board Interconnects In Microprocessor-Based Systems. Asian Test Symposium 1996: 56-61
6		Sying-Jyan Wang: Load-Balancing in Multistage Interconnection Networks under Multiple-Pass Routing. J. Parallel Distrib. Comput. 36(2): 189-194 (1996)
1994
5		Sying-Jyan Wang: Synthesis of Sequential Machines with Reduced Testing Cost. EDAC-ETC-EUROASIC 1994: 302-306
4		Sying-Jyan Wang, Niraj K. Jha: Algorithm-Based Fault Tolerance for FFT Networks. IEEE Trans. Computers 43(7): 849-854 (1994)
1993
3	EE	Niraj K. Jha, Sying-Jyan Wang: Design and synthesis of self-checking VLSI circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 12(6): 878-887 (1993)
1992
2		Niraj K. Jha, Sying-Jyan Wang, Phillip C. Gripka: Multiple Input Bridging Fault Detection in CMOS Sequential Circuits. ICCD 1992: 369-372
1991
1		Niraj K. Jha, Sying-Jyan Wang: Design and Synthesis of Self-Checking VLSI Circuits and Systems. ICCD 1991: 578-581

Coauthor Index

1	Shih-Cheng Chen	[24]
2	Yan-Ting Chen	[21]
3	Sheng-Nan Chiou	[14]
4	Yu-Hsuan Fu	[17] [19]
5	Phillip C. Gripka	[2]
6	Kuang-Cyun Hsiao	[23]
7	Po-Ching Hsu	[7]
8	Yu-Lung Hsu	[15]
9	Chao-Neng Huang	[10]
10	Niraj K. Jha	[1] [2] [3] [4]
11	Nan-Cheng Lai	[17]
12	Katherine Shu-Min Li	[21] [23] [24]
13	Nan-Cheng Li	[16]
14	Chia-Chun Lien	[11]
15	Ching-Hung Lin	[20]
16	Yen-Nan Lin	[18]
17	Kuo-Lin Peng	[23]
18	Po-Chang Tsai	[20]
19	Tsi-Ming Tsai	[9]
20	Chen-Jung Wei	[12]
21	Ming-Chen Wen	[18]
22	Tung-Hua Yeh	[20] [22]

Colors in the list of coauthors