| 2001 |
|---|
| 9 | EE | Kiran Bondalapati:
Parallelizing DSP Nested Loops on Reconfigurable Architectures using Data Context Switching.
DAC 2001: 273-276 |
| 2000 |
|---|
| 8 | EE | Neungsoo Park,
Dongsoo Kang,
Kiran Bondalapati,
Viktor K. Prasanna:
Dynamic Data Layouts for Cache-Conscious Factorization of DFT.
IPDPS 2000: 693-702 |
| 7 | EE | Kiran Bondalapati,
Viktor K. Prasanna:
Loop Pipelining and Optimization for Run Time Reconfiguration.
IPDPS Workshops 2000: 906-915 |
| 1999 |
|---|
| 6 | EE | Kiran Bondalapati,
Viktor K. Prasanna:
Dynamic Precision Management for Loop Computations on Reconfigurable Architectures.
FCCM 1999: 249- |
| 5 | | Kiran Bondalapati,
Viktor K. Prasanna:
DRIVE: An Interpretive Simulation and Visualization Environment for Dynamically Reconfigurable Systems.
FPL 1999: 31-40 |
| 4 | | Kiran Bondalapati,
Pedro C. Diniz,
Phillip Duncan,
John J. Granacki,
Mary W. Hall,
Rajeev Jain,
Heidi E. Ziegler:
DEFACTO: A Design Environment for Adaptive Computing Technology.
IPPS/SPDP Workshops 1999: 570-578 |
| 3 | | Kiran Bondalapati,
Viktor K. Prasanna:
Hardware Object Selection for Mapping Loops onto Reconfigurable Architectures.
PDPTA 1999: 1104-1110 |
| 1998 |
|---|
| 2 | EE | Kiran Bondalapati,
Viktor K. Prasanna:
Mapping Loops onto Reconfigurable Architectures.
FPL 1998: 268-277 |
| 1997 |
|---|
| 1 | EE | Ram Kesavan,
Kiran Bondalapati,
Dhabaleswar K. Panda:
Multicast on Irregular Switch-Based Networks with Wormhole Routing.
HPCA 1997: 48-57 |
