Bing J. Sheu

2002
29	EE	Yoondong Park, Steve H. Jen, Bing J. Sheu, Heesook Yoon, In Gyeom Kim: An efficient parameter extraction method using statistical optimization in S-CMOS deep-submicron/nanometer model. ISCAS (5) 2002: 233-236
2001
28	EE	Andrew B. Kahng, Bing J. Sheu, Nancy Nettleton, John M. Cohn, Shekhar Borkar, Louis Scheffer, Ed Cheng, Sang Wang: Panel: Is Nanometer Design Under Control? DAC 2001: 591-592
2000
27	EE	Yoondong Park, Jim-Shih Liaw, Theodore W. Berger, Bing J. Sheu: Compact VLSI Neural Network Circuit with High-Capacity Dynamic Synapses. IJCNN (4) 2000: 214-218
1998
26	EE	Steve H. Jen, Bing J. Sheu: A compact and unified MOS DC current model with highly continuous conductances for low-voltage ICs. IEEE Trans. on CAD of Integrated Circuits and Systems 17(2): 169-172 (1998)
1997
25		Wai-Chi Fang, Guang Yang, Bedabrata Pain, Bing J. Sheu: A Low Power Smart Vision System Based on Active Pixel Sensor Integrated with Programmable Neural Processor. ICCD 1997: 429-434
1996
24	EE	David C. Chen, Bing J. Sheu, Theodore W. Berger: A Compact Neural Network Based CDMA Receiver for Multimedia Wireless Communication. ICCD 1996: 99-
1995
23	EE	Eric Y. Chou, Bing J. Sheu, Tony H. Wu, Robert C. Chang: VLSI design of densely-connected array processors. ICCD 1995: 492-497
22	EE	Wai-Chi Fang, Bing J. Sheu, Holger Venus, Rainer Sandau: Smart-pixel array processors based on optimal cellular neural networks for space sensor applications. ICCD 1995: 703-
21		Bing J. Sheu, Robert C. Chang, Tony H. Wu, Sa Hyun Bang: VLSI-Compatible Cellular Neural Networks with Optimal Solution Capability for Optimization. ISCAS 1995: 1165-1168
20		Bing J. Sheu, Theodore W. Berger, Tony H. Wu, Richard H. Tsai: VLSI Neural Network Implementation of a Hippocampal Model. ISCAS 1995: 1664-1667
19		Bing J. Sheu: Constructing Intelligent Microsystems with Modular VLSI Networks Design. ISCAS 1995: 2100-2103
18		Bing J. Sheu, Sa Hyun Bang, Wai-Chi Fang: VLSI Design of Cellular Neutral Networks with Annealing and Optical Input Capabilities. ISCAS 1995: 653-656
1994
17		Robert C.-H. Chang, Bing J. Sheu: An Analog MOS Model for Circuit Simulation and Benchmark Test Results. ISCAS 1994: 311-314
16		Sa Hyun Bang, Bing J. Sheu, Josephine C.-F. Chang: Search of Optimal Solutions in Multi-Level Neural Networks. ISCAS 1994: 423-426
15		Joongho Choi, Bing J. Sheu, Josephine C.-F. Chang: A Gaussian Synapse Circuit for Analog VLSI Neural Networks. ISCAS 1994: 483-486
14	EE	Joongho Choi, Bing J. Sheu, Josephine C.-F. Chang: A Gaussian synapse circuit for analog VLSI neural networks. IEEE Trans. VLSI Syst. 2(1): 129-133 (1994)
13	EE	Wai-Chi Fang, Chi-Yung Chang, Bing J. Sheu, Oscal T.-C. Chen, J. C. Curlander: VLSI systolic binary tree-searched vector quantizer for image compression. IEEE Trans. VLSI Syst. 2(1): 33-44 (1994)
12	EE	Sudhir M. Gowda, Bing J. Sheu: BSIM plus: an advanced SPICE model for submicron MOS VLSI circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 13(9): 1166-1170 (1994)
11	EE	Sudhir M. Gowda, Bing J. Sheu, Wen-Jay Hsu: Testing of programmable analog neural network chips. VLSI Signal Processing 8(3): 267-282 (1994)
1993
10	EE	Ji-chien Lee, Bing J. Sheu, Rama Chellappa: A VLSI neuroprocessor for image restoration using analog computing-based systolic architecture. VLSI Signal Processing 5(2-3): 185-199 (1993)
9	EE	Ji-chien Lee, Bing J. Sheu, Rama Chellappa: A mixed-signal VLSI competitive neuroprocessor for video motion detection. VLSI Signal Processing 6(1): 57-66 (1993)
1992
8		Oscal T.-C. Chen, Z. Zhang, Bing J. Sheu: An Adaptive High-Speed Lossy Data Compression. Data Compression Conference 1992: 349-358
7		Oscal T.-C. Chen, Bing J. Sheu, Wai-Chi Fang: Image Compression on a VLSI Neural-Based Vector Quantizer. Inf. Process. Manage. 28(6): 687-706 (1992)
1991
6		Wai-Chi Fang, Bing J. Sheu, Oscal T.-C. Chen: A Neural Network Based VLSI Vector Quantizer for Real-Time Image Compression. Data Compression Conference 1991: 342-351
5		Wen-Jay Hsu, Bing J. Sheu, Sudhir M. Gowda: Testing of Analog Neural Array-Processor Chips. ICCD 1991: 118-121
4		Joongho Choi, Bing J. Sheu: A GaAs Receiver Module for Optoelectronic Computing and Interconnection. ICCD 1991: 494-497
1988
3	EE	Bing J. Sheu, Wen-Jay Hsu, P. K. Ko: An MOS transistor charge model for VLSI design. IEEE Trans. on CAD of Integrated Circuits and Systems 7(4): 520-527 (1988)
2	EE	Chung-Ping Wan, Bing J. Sheu, Shih-Lien Lu: Device and circuit simulation interface for an integrated VLSI design environment. IEEE Trans. on CAD of Integrated Circuits and Systems 7(9): 998-1004 (1988)
1987
1	EE	M. C. Hsu, Bing J. Sheu: Inverse-Geometry Dependence of MOS Transistor Electrical Parameters. IEEE Trans. on CAD of Integrated Circuits and Systems 6(4): 582-585 (1987)

Coauthor Index

1	Sa Hyun Bang	[16] [18] [21]
2	Theodore W. Berger	[20] [24] [27]
3	Shekhar Y. Borkar (Shekhar Borkar)	[28]
4	Chi-Yung Chang	[13]
5	Josephine C.-F. Chang	[14] [15] [16]
6	Robert C. Chang	[21] [23]
7	Robert C.-H. Chang	[17]
8	Rama Chellappa	[9] [10]
9	David C. Chen	[24]
10	Oscal T.-C. Chen	[6] [7] [8] [13]
11	Ed Cheng	[28]
12	Joongho Choi	[4] [14] [15]
13	Eric Y. Chou	[23]
14	John M. Cohn	[28]
15	J. C. Curlander	[13]
16	Wai-Chi Fang	[6] [7] [13] [18] [22] [25]
17	Sudhir M. Gowda	[5] [11] [12]
18	M. C. Hsu	[1]
19	Wen-Jay Hsu	[3] [5] [11]
20	Steve H. Jen	[26] [29]
21	Andrew B. Kahng	[28]
22	In Gyeom Kim	[29]
23	P. K. Ko	[3]
24	Ji-chien Lee	[9] [10]
25	Jim-Shih Liaw	[27]
26	Shih-Lien Lu	[2]
27	Nancy Nettleton	[28]
28	Bedabrata Pain	[25]
29	Yoondong Park	[27] [29]
30	Rainer Sandau	[22]
31	Louis Scheffer	[28]
32	Richard H. Tsai	[20]
33	Holger Venus	[22]
34	Chung-Ping Wan	[2]
35	Sang Wang	[28]
36	Tony H. Wu	[20] [21] [23]
37	Guang Yang	[25]
38	Heesook Yoon	[29]
39	Z. Zhang	[8]

Colors in the list of coauthors