Ki-Seok Chung

2008
16	EE	Young-Si Hwang, Sung-Kwan Ku, Chan-Min Jung, Ki-Seok Chung: Predictive power aware management for embedded mobile devices. ASP-DAC 2008: 36-41
15	EE	Sung-Kwan Ku, Han-Sam Jung, Ki-Seok Chung: A unified power measurement and management platform for pipelined MPSoC executions. SoCC 2008: 13-16
2007
14	EE	Young-Geun Lee, Joo-Yul Park, Ki-Seok Chung: Design of Low Power MAC Operator with Dual Precision Mode. RTCSA 2007: 309-318
2004
13	EE	Jaewon Seo, Taewhan Kim, Ki-Seok Chung: Profile-based optimal intra-task voltage scheduling for hard real-time applications. DAC 2004: 87-92
2003
12		J. K. Kim, S. H. Won, Ki-Seok Chung, H. D. Cho, T. W. Kang, T. S. Nam, C. S. Kang, C. H. Yi, D. S. Kim: Properties of A1/BaTa2O6/GaN MIS Structure. VLSI 2003: 240-243
2002
11	EE	Unni Narayanan, Ki-Seok Chung, Taewhan Kim: Enhanced bus invert encodings for low-power. ISCAS (5) 2002: 25-28
10	EE	Ki-Seok Chung, Taewhan Kim, C. L. Liu: A Complete Model for Glitch Analysis in Logic Circuits. Journal of Circuits, Systems, and Computers 11(2): 137-154 (2002)
9	EE	Ki-Seok Chung, Rajesh K. Gupta, Taewhan Kim, C. L. Liu: Synthesis and Optimization of Combinational Interface Circuits. VLSI Signal Processing 31(3): 243-261 (2002)
2001
8	EE	Taewhan Kim, Ki-Seok Chung, Chien-Liang Liu: A Static Estimation Technique of Power Sensitivity in Logic Circuits. DAC 2001: 215-219
7	EE	Ki-Seok Chung, Taewhan Kim, C. L. Liu: G-vector: A New Model for Glitch Analysis in Logic Circuits. VLSI Signal Processing 27(3): 235-251 (2001)
2000
6	EE	Ki-Seok Chung, Taewhan Kim, Chien-Liang Liu: Behavioral-level partitioning for low power design in control-dominated application. ACM Great Lakes Symposium on VLSI 2000: 156-161
5	EE	Sungpack Hong, Taewhan Kim, Unni Narayanan, Ki-Seok Chung: Decomposition of Bus-Invert Coding for Low-Power I/O. Journal of Circuits, Systems, and Computers 10(1-2): 101-112 (2000)
1998
4	EE	Ki-Seok Chung, C. L. Liu: Local transformation techniques for multi-level logiccircuits utilizing circuit symmetries for power reduction. ISLPED 1998: 215-220
1997
3	EE	Unni Narayanan, Hon Wai Leong, Ki-Seok Chung, Chien-Liang Liu: Low power multiplexer decomposition. ISLPED 1997: 269-274
1996
2	EE	Ki-Seok Chung, Rajesh K. Gupta, C. L. Liu: An algorithm for synthesis of system-level interface circuits. ICCAD 1996: 442-447
1994
1		Taewhan Kim, Ki-Seok Chung, Chien-Liang Liu: A Stepwise Refinement Data Path Synthesis Procedure for Easy Testability. EDAC-ETC-EUROASIC 1994: 586-590

Coauthor Index

1	H. D. Cho	[12]
2	Rajesh K. Gupta (Rajesh Gupta)	[2] [9]
3	Sungpack Hong	[5]
4	Young-Si Hwang	[16]
5	Chan-Min Jung	[16]
6	Han-Sam Jung	[15]
7	C. S. Kang	[12]
8	T. W. Kang	[12]
9	D. S. Kim	[12]
10	J. K. Kim	[12]
11	Taewhan Kim	[1] [5] [6] [7] [8] [9] [10] [11] [13]
12	Sung-Kwan Ku	[15] [16]
13	Young-Geun Lee	[14]
14	Hon Wai Leong (Hon-Wai Leong)	[3]
15	C. L. Liu (Chung Laung (Dave) Liu)	[2] [4] [7] [9] [10]
16	Chien-Liang Liu	[1] [3] [6] [8]
17	T. S. Nam	[12]
18	Unni Narayanan	[3] [5] [11]
19	Joo-Yul Park	[14]
20	Jaewon Seo	[13]
21	S. H. Won	[12]
22	C. H. Yi	[12]

Colors in the list of coauthors