Emil Gizdarski

2008
16	EE	Emil Gizdarski: Constructing Augmented Multimode Compactors. VTS 2008: 29-34
2007
15	EE	Peter Wohl, John A. Waicukauski, Rohit Kapur, S. Ramnath, Emil Gizdarski, Thomas W. Williams, P. Jaini: Minimizing the Impact of Scan Compression. VTS 2007: 67-74
2005
14	EE	Peter Wohl, John A. Waicukauski, Sanjay Patel, Cy Hay, Emil Gizdarski, Ben Mathew: Hierarchical Compactor Design for Diagnosis in Deterministic Logic BIST. VTS 2005: 359-365
2004
13	EE	Davide Appello, Alessandra Fudoli, Katia Giarda, Emil Gizdarski, Ben Mathew, Vincenzo Tancorre: Yield Analysis of Logic Circuits. VTS 2004: 103-108
12	EE	Nodari Sitchinava, Samitha Samaranayake, Rohit Kapur, Emil Gizdarski, Frederic Neuveux, Thomas W. Williams: Changing the Scan Enable during Shift. VTS 2004: 73-78
11	EE	Davide Appello, Alessandra Fudoli, Katia Giarda, Vincenzo Tancorre, Emil Gizdarski, Ben Mathew: Understanding Yield Losses in Logic Circuits. IEEE Design & Test of Computers 21(3): 208-215 (2004)
2003
10	EE	Samitha Samaranayake, Emil Gizdarski, Nodari Sitchinava, Frederic Neuveux, Rohit Kapur, Thomas W. Williams: A Reconfigurable Shared Scan-in Architecture. VTS 2003: 9-14
2002
9	EE	Emil Gizdarski, Hideo Fujiwara: Fault Set Partition for Efficient Width Compression. Asian Test Symposium 2002: 194-199
8	EE	Emil Gizdarski, Hideo Fujiwara: SPIRIT: a highly robust combinational test generation algorithm. IEEE Trans. on CAD of Integrated Circuits and Systems 21(12): 1446-1458 (2002)
7	EE	Michiko Inoue, Emil Gizdarski, Hideo Fujiwara: Sequential Circuits with Combinational Test Generation Complexity under Single-Fault Assumption. J. Electronic Testing 18(1): 55-62 (2002)
2001
6	EE	Emil Gizdarski, Hideo Fujiwara: A Framework for Low Complexity Static Learning. DAC 2001: 546-549
5	EE	Emil Gizdarski, Hideo Fujiwara: SPIRIT: A Highly Robust Combinational Test Generation Algorithm. VTS 2001: 346-351
2000
4	EE	Emil Gizdarski, Hideo Fujiwara: Spirit: satisfiability problem implementation for redundancy identification and test generation. Asian Test Symposium 2000: 171-178
3	EE	Michiko Inoue, Emil Gizdarski, Hideo Fujiwara: A class of sequential circuits with combinational test generation complexity under single-fault assumption. Asian Test Symposium 2000: 398-403
2	EE	Emil Gizdarski: Detection of Delay Faults in Memory Address Decoders. J. Electronic Testing 16(4): 381-387 (2000)
1996
1	EE	Emil Gizdarski: Built-in self-test for folded bit-line Mbit DRAMs. Integration 21(1-2): 95-112 (1996)

Coauthor Index

1	Davide Appello	[11] [13]
2	Alessandra Fudoli	[11] [13]
3	Hideo Fujiwara	[3] [4] [5] [6] [7] [8] [9]
4	Katia Giarda	[11] [13]
5	Cy Hay	[14]
6	Michiko Inoue	[3] [7]
7	P. Jaini	[15]
8	Rohit Kapur	[10] [12] [15]
9	Ben Mathew	[11] [13] [14]
10	Frederic Neuveux	[10] [12]
11	Sanjay Patel	[14]
12	S. Ramnath	[15]
13	Samitha Samaranayake	[10] [12]
14	Nodari Sitchinava	[10] [12]
15	Vincenzo Tancorre	[11] [13]
16	John A. Waicukauski	[14] [15]
17	Thomas W. Williams	[10] [12] [15]
18	Peter Wohl	[14] [15]

Colors in the list of coauthors