2008 |
58 | EE | Veerapaneni Nagbhushan,
C. Y. Roger Chen:
Modeling and reduction of complex timing constraints in high performance digital circuits.
ICCD 2008: 544-550 |
2007 |
57 | EE | Ting Wei Chiang,
C. Y. Roger Chen,
Wei-Yu Chen:
A technique for selecting CMOS transistor orders.
ICCD 2007: 438-443 |
56 | EE | Veerapaneni Nagbhushan,
C. Y. Roger Chen:
Algorithms to simplify multi-clock/edge timing constraints.
ICCD 2007: 444-449 |
55 | EE | Ting Wei Chiang,
C. Y. Roger Chen,
Wei-Yu Chen:
An efficient gate delay model for VLSI design.
ICCD 2007: 450-455 |
2003 |
54 | EE | Bharat Krishna,
C. Y. Roger Chen,
Naresh Sehgal:
A novel ultra-fast heuristic for VLSI CAD steiner trees.
ACM Great Lakes Symposium on VLSI 2003: 192-197 |
53 | EE | Bill Halpin,
Naresh Sehgal,
C. Y. Roger Chen:
Detailed Placement with Net Length Constraints.
IWSOC 2003: 22-27 |
2001 |
52 | EE | Bill Halpin,
C. Y. Roger Chen,
Naresh Sehgal:
Timing Driven Placement using Physical Net Constraints.
DAC 2001: 780-783 |
2000 |
51 | EE | Bill Halpin,
C. Y. Roger Chen,
Naresh Sehgal:
A sensitivity based placer for standard cells.
ACM Great Lakes Symposium on VLSI 2000: 193-196 |
50 | EE | Bharat Krishna,
C. Y. Roger Chen,
Naresh Sehgal:
A novel technique for sea of gates global routing.
ACM Great Lakes Symposium on VLSI 2000: 71-74 |
49 | | Dikran S. Meliksetian,
Frank Feng-Kuo Yu,
C. Y. Roger Chen:
Methodologies for Designing Video Servers.
IEEE Transactions on Multimedia 2(1): 62-69 (2000) |
48 | | Muhammad Naeem Ayyaz,
Dikran S. Meliksetian,
C. Y. Roger Chen:
Partitionable multistage interconnection networks. Part 2: Task migration schemes.
Telecommunication Systems 13(1): 45-67 (2000) |
1999 |
47 | EE | Bradley S. Carlson,
C. Y. Roger Chen,
Dikran S. Meliksetian:
Transistor Chaining in Static CMOS Functional Cells of Arbitrary Planar Topology.
Discrete Applied Mathematics 90(1-3): 89-114 (1999) |
1998 |
46 | | Bharat Krishna,
C. Y. Roger Chen,
Naresh Sehgal:
Technique for Planning of Terminal Locations of Leaf Cells in Cell-Based Design with Routing Considerations.
VLSI Design 1998: 53-58 |
45 | | Muhammad Naeem Ayyaz,
Dikran S. Meliksetian,
C. Y. Roger Chen:
Partitionable multistage interconnection networks. Part 1: Dynamic subcube compaction.
Telecommunication Systems 10(1): 79-106 (1998) |
1997 |
44 | | Tacettin Kiprulu,
Dikran S. Meliksetian,
C. Y. Roger Chen:
Smoothing Algorithms for the Delivery of Compressed Video.
ICC (3) 1997: 1330-1334 |
1996 |
43 | EE | Bradley S. Carlson,
C. Y. Roger Chen,
Dikran S. Meliksetian:
Transistor Chaining in CMOS Leaf Cells of Planar Topology.
Great Lakes Symposium on VLSI 1996: 194-199 |
1995 |
42 | | Calvin J. A. Hsia,
C. Y. Roger Chen:
Synthesis of Asynchronous Circuits - Testing Unique Circuit Behavior of Signal Transition Graphs.
ISCAS 1995: 1074-1077 |
41 | EE | Qinghong Wu,
C. Y. Roger Chen,
Bradley S. Carlson:
LILA: layout generation for iterative logic arrays.
IEEE Trans. on CAD of Integrated Circuits and Systems 14(11): 1359-1369 (1995) |
40 | EE | C. Y. Roger Chen,
Cliff Yungchin Hou,
Bradley S. Carlson:
A preprocessor for improving channel routing hierarchical pin permutation.
IEEE Trans. on CAD of Integrated Circuits and Systems 14(7): 896-903 (1995) |
39 | EE | C. Y. Roger Chen,
Cliff Yungchin Hou:
A pin permutation algorithm for improving over-the-cell channel routing.
IEEE Trans. on CAD of Integrated Circuits and Systems 14(8): 1030-1037 (1995) |
38 | EE | C. Y. Roger Chen,
Shuo-Hsien Hsiao,
Abdulaziz S. Almazyad:
A new model for the performance evaluation of synchronous circuit switched multistage interconnection networks.
IEEE/ACM Trans. Netw. 3(6): 708-715 (1995) |
37 | EE | C. Y. Roger Chen,
Georges A. Makhoul,
Dikran S. Meliksetian:
A queueing analysis of the performance of DQDB.
IEEE/ACM Trans. Netw. 3(6): 872-881 (1995) |
36 | EE | Arif Ghafoor,
C. Y. Roger Chen:
Special Issue on Multimedia Processing and Technology.
J. Parallel Distrib. Comput. 30(2): 107-110 (1995) |
35 | | C. Y. Roger Chen,
Dikran S. Meliksetian,
M. C. Chang,
L. J. Liu:
Design of a Multimedia Object-Oriented DBMS.
Multimedia Syst. 3(5-6): 217-227 (1995) |
34 | EE | Bradley S. Carlson,
C. Y. Roger Chen,
Dikran S. Meliksetian:
Dual Eulerian Properties of Plane Multigraphs.
SIAM J. Discrete Math. 8(1): 33-50 (1995) |
1994 |
33 | EE | Mohammed Aloqeely,
C. Y. Roger Chen:
Sequencer-Based Data Path Synthesis of Regular Iterative Algorithms.
DAC 1994: 155-160 |
32 | | Muhammad K. Dhodhi,
Imtiaz Ahmad,
C. Y. Roger Chen:
Synthesis of Application-Specific Multiprocessor Systems.
EDAC-ETC-EUROASIC 1994: 671 |
31 | EE | C. Y. Roger Chen,
Mohammed Aloqeely:
A new technique for exploiting regularity in data path synthesis.
EURO-DAC 1994: 394-399 |
30 | EE | Naresh Sehgal,
C. Y. Roger Chen,
John M. Acken:
An object-oriented cell library manager.
ICCAD 1994: 750-753 |
29 | | Qinghong Wu,
C. Y. Roger Chen,
John M. Acken:
Efficent Boolean Matching Algorithm for Cell Libraries.
ICCD 1994: 36-39 |
28 | | Naresh Kumar Seghal,
C. Y. Roger Chen,
John M. Acken:
A High Performance General Purpose Multi-Point Signal Router.
ISCAS 1994: 475-478 |
27 | | Abdulaziz S. Mazyad,
C. Y. Roger Chen:
Performance Evaluation of HIPPI Interconnection System Using a Camp-On Strategy.
LCN 1994: 20-29 |
26 | EE | C. Y. Roger Chen,
Cliff Yungchin Hou,
Uminder Singh:
Optimal algorithms for bubble sort based non-Manhattan channel routing.
IEEE Trans. on CAD of Integrated Circuits and Systems 13(5): 603-609 (1994) |
25 | EE | James V. Luciani,
C. Y. Roger Chen:
An analytical model for partially blocking finite-buffered switching networks.
IEEE/ACM Trans. Netw. 2(5): 533-540 (1994) |
24 | | Kingsley C. Nwosu,
C. Y. Roger Chen,
P. Bruce Berra:
Multimedia Object Modeling and Storage Allocation Strategies.
J. Intell. Inf. Syst. 3(3/4): 357-398 (1994) |
1993 |
23 | EE | Bradley S. Carlson,
C. Y. Roger Chen:
Performance Enhancement of CMOS VLSI Circuits by Transistor Reordering.
DAC 1993: 361-366 |
22 | | C. Y. Roger Chen,
Kingsley C. Nwosu,
P. Bruce Berra:
Modeling and Storage Allocation Strategies for Homogeneous Parallel Access Storage Devices in Real Time Multimedia Information Processing.
ICCI 1993: 565-569 |
21 | | Shuo-Hsien Hsiao,
C. Y. Roger Chen:
A New Model for the Performance Evaluation of Synchronous Circuit Switched Multistage Interconnection Networks.
IPPS 1993: 773-777 |
20 | | Dikran S. Meliksetian,
C. Y. Roger Chen:
A Markov-Modulated Bernoulli Process Approximation for the Analysis of Banyan Networks.
SIGMETRICS 1993: 183-194 |
19 | EE | Dikran S. Meliksetian,
C. Y. Roger Chen:
Optimal Routing Algorithm and the Diameter of the Cube-Connected Cycles.
IEEE Trans. Parallel Distrib. Syst. 4(10): 1172-1178 (1993) |
1992 |
18 | EE | Cliff Yungchin Hou,
C. Y. Roger Chen:
A Pin Permutation Algorithm for Improving Over-the-Cell Channel Routing.
DAC 1992: 594-599 |
17 | | P. Bruce Berra,
C. Y. Roger Chen,
Arif Ghafoor,
Thomas D. C. Little:
Issues in Networking and Data Management of Distributed Multimedia Systems.
HPDC 1992: 4-15 |
16 | | Muhammad F. Mudawwar,
C. Y. Roger Chen:
The Signal Flow Model: A novel Data Driven Approach to Parallel Processing.
ICPP (1) 1992: 196-200 |
15 | | Dikran S. Meliksetian,
C. Y. Roger Chen:
Performance Analysis of Communications in Static Interconnection Networks.
SIGMETRICS 1992: 249-250 |
14 | EE | Shuo-Hsien Hsiao,
C. Y. Roger Chen:
Performance Evaluation of Circuit Switched Multistage Interconnection Networks Using a Hold Strategy.
IEEE Trans. Parallel Distrib. Syst. 3(5): 632-640 (1992) |
13 | EE | Uminder Singh,
C. Y. Roger Chen:
From logic to symbolic layout for gate matrix.
IEEE Trans. on CAD of Integrated Circuits and Systems 11(2): 216-227 (1992) |
1991 |
12 | EE | C. Y. Roger Chen,
Michael Z. Moricz:
Datapath Scheduling for Two-Level Pipelining.
DAC 1991: 603-606 |
11 | | Imtiaz Ahmad,
C. Y. Roger Chen:
Post-Processor for Data Path Synthesis Using Multiport Memories.
ICCAD 1991: 276-279 |
10 | | Cliff Yungchin Hou,
C. Y. Roger Chen:
A Hierarchical Methodology to Improve Channel Routing by Pin Permutation.
ICCAD 1991: 440-443 |
9 | EE | Thomas D. C. Little,
C. Y. Roger Chen,
C. S. Chang,
P. Bruce Berra:
Multimedia Synchronization.
IEEE Data Eng. Bull. 14(3): 26-35 (1991) |
8 | EE | C. Y. Roger Chen,
Michael Z. Moricz:
A delay distribution methodology for the optimal systolic synthesis of linear recurrence algorithms.
IEEE Trans. on CAD of Integrated Circuits and Systems 10(6): 685-697 (1991) |
7 | EE | Bradley S. Carlson,
C. Y. Roger Chen,
Uminder Singh:
Optimal cell generation for dual independent layout styles.
IEEE Trans. on CAD of Integrated Circuits and Systems 10(6): 770-782 (1991) |
1990 |
6 | EE | Uminder Singh,
C. Y. Roger Chen:
A Transistor Reordering Technique for Gate Matrix Layout.
DAC 1990: 462-467 |
5 | | Calvin J. A. Hsia,
C. Y. Roger Chen:
Permutation Capability of Multistage Interconnection Networks.
ICPP (1) 1990: 338-346 |
4 | | Dikran S. Meliksetian,
C. Y. Roger Chen:
Communication Aspects of the Cube Connected Cycles.
ICPP (1) 1990: 579-580 |
3 | | C. Y. Roger Chen,
Yeh-Ching Chung:
Embedding Networks with Ring Connections in Hypercube Machines.
ICPP (3) 1990: 327-334 |
2 | EE | P. Bruce Berra,
C. Y. Roger Chen,
Arif Ghafoor,
C. C. Lin,
Thomas D. C. Little,
D. Shin:
Architecture for distributed multimedia database systems.
Computer Communications 13(4): 217-231 (1990) |
1988 |
1 | EE | C. Y. Roger Chen:
TOBOL - a new methodology for the top-to-bottom level hardware description in VLSI design-automation systems.
ICCL 1988: 404-411 |