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Rajeev Jayaraman

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2002
6EEMajid Sarrafzadeh, Rajeev Jayaraman: Guest editorial. ACM Trans. Design Autom. Electr. Syst. 7(4): 499-500 (2002)
2001
5EERob A. Rutenbar, Max Baron, Thomas Daniel, Rajeev Jayaraman, Zvi Or-Bach, Jonathan Rose, Carl Sechen: Panel: (When) Will FPGAs Kill ASICs? DAC 2001: 321-322
4EERajeev Jayaraman: Physical design for FPGAs. ISPD 2001: 214-221
2000
3EEJason Helge Anderson, Jim Saunders, Sudip Nag, Chari Madabhushi, Rajeev Jayaraman: A Placement Algorithm for FPGA Designs with Multiple I/O Standards. FPL 2000: 211-220
1998
2EEEmil S. Ochotta, Patrick J. Crotty, Charles R. Erickson, Chih-Tsung Huang, Rajeev Jayaraman, Richard C. Li, Joseph D. Linoff, Luan Ngo, Hy V. Nguyen, Kerry M. Pierce, Douglas P. Wieland, Jennifer Zhuang, Scott S. Nance: A Novel Predictable Segmented FPGA Routing Architecture. FPGA 1998: 3-11
1991
1 Rajeev Jayaraman, Rob A. Rutenbar: A Parallel Steiner Heuristic for Wirelength Estimation of Large Net Populations. ICCAD 1991: 344-347

Coauthor Index

1Jason Helge Anderson [3]
2Max Baron [5]
3Patrick J. Crotty [2]
4Thomas Daniel [5]
5Charles R. Erickson [2]
6Chih-Tsung Huang [2]
7Richard C. Li [2]
8Joseph D. Linoff [2]
9Chari Madabhushi [3]
10Sudip Nag [3]
11Scott S. Nance [2]
12Luan Ngo [2]
13Hy V. Nguyen [2]
14Emil S. Ochotta [2]
15Zvi Or-Bach [5]
16Kerry M. Pierce [2]
17Jonathan Rose [5]
18Rob A. Rutenbar [1] [5]
19Majid Sarrafzadeh [6]
20Jim Saunders [3]
21Carl Sechen [5]
22Douglas P. Wieland [2]
23Jennifer Zhuang [2]

Colors in the list of coauthors

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)