P. S. Dasgupta
List of publications from the
2009 |
23 | EE | Tuhina Samanta,
Hafizur Rahaman,
Prasun Ghosal,
Parthasarathi Dasgupta:
A Method for the Multi-Net Multi-Pin Routing Problem with Layer Assignment.
VLSI Design 2009: 387-392 |
22 | EE | Sriparna Saha,
Susmita Sur-Kolay,
Parthasarathi Dasgupta,
Sanghamitra Bandyopadhyay:
MAkE: Multiobjective algorithm for k-way equipartitioning of a point set.
Appl. Soft Comput. 9(2): 711-724 (2009) |
2008 |
21 | EE | Prasun Ghosal,
Tuhina Samanta,
Hafizur Rahaman,
Parthasarathi Dasgupta:
Thermal-Aware Placement of Standard Cells and Gate Arrays: Studies and Observations.
ISVLSI 2008: 369-374 |
20 | EE | Tuhina Samanta,
Prasun Ghosal,
Hafizur Rahaman,
Parthasarathi Dasgupta:
Revisiting fidelity: a case of elmore-based Y-routing trees.
SLIP 2008: 27-34 |
2007 |
19 | EE | Debasri Saha,
Parthasarathi Dasgupta,
Susmita Sur-Kolay,
Samar Sen-Sarma:
A Novel Scheme for Encoding and Watermark Embedding in VLSI Physical Design for IP Protection.
ICCTA 2007: 111-116 |
18 | EE | Tuhina Samanta,
Prasun Ghosal,
Hafizur Rahaman,
Parthasarathi Dasgupta:
Minimum-Congestion Placement for Y-interconnects: Some studies and observations.
ISVLSI 2007: 73-80 |
2006 |
17 | EE | Sriparna Saha,
Susmita Sur-Kolay,
Sanghamitra Bandyopadhyay,
Parthasarathi Dasgupta:
Multiobjective Genetic Algorithm for k-way Equipartitioning of a Point Set with Application to CAD-VLSI.
ICIT 2006: 281-284 |
16 | EE | Tuhina Samanta,
Prasun Ghosal,
Hafizur Rahaman,
Parthasarathi Dasgupta:
A heuristic method for constructing hexagonal Steiner minimal trees for routing in VLSI.
ISCAS 2006 |
15 | EE | Parthasarathi Dasgupta,
Prashant Yadava:
Linear Required-Arrival-Time Trees and their Construction.
VLSI Design 2006: 790-793 |
2005 |
14 | | Prasun Ghosal,
Tuhina Samanta,
Hafizur Rahaman,
Parthasarathi Dasgupta:
Recent Trends in the Application of Meta-Heuristics to VLSI Layout Design.
IICAI 2005: 232-251 |
13 | EE | Parthasarathi Dasgupta:
Revisiting VLSI Interconnects in Deep Sub-Micron: Some Open Questions.
VLSI Design 2005: 615-620 |
2004 |
12 | EE | Susmita Sur-Kolay,
Parthasarathi Dasgupta,
Bhargab B. Bhattacharya,
Sujit T. Zachariah:
Physical Design Trends and Layout-Based Fault Modeling.
VLSI Design 2004: 6-8 |
2003 |
11 | EE | Parthasarathi Dasgupta,
Andrew B. Kahng,
Swamy Muddu:
A Novel Metric for Interconnect Architecture Performance.
DATE 2003: 10448-10455 |
10 | | Parthasarathi Dasgupta:
Range-Based Discrepancy Search with Applications to VLSI Design.
IICAI 2003: 621-631 |
2002 |
9 | EE | Parthasarathi Dasgupta,
Peichen Pan,
Subhas C. Nandy,
Bhargab B. Bhattacharya:
Monotone bipartitioning problem in a planar point set with applications to VLSI.
ACM Trans. Design Autom. Electr. Syst. 7(2): 231-248 (2002) |
2001 |
8 | EE | Koushik Sinha,
Susmita Sur-Kolay,
Bhargab B. Bhattacharya,
P. S. Dasgupta:
Partitioning Routing Area into Zones with Distinct Pins.
VLSI Design 2001: 345- |
7 | EE | Parthasarathi Dasgupta,
Susmita Sur-Kolay:
Slicible rectangular graphs and their optimal floorplans.
ACM Trans. Design Autom. Electr. Syst. 6(4): 447-470 (2001) |
6 | | Parthasarathi Dasgupta,
Anup K. Sen,
Subhas C. Nandy,
Bhargab B. Bhattacharya:
Searching networks with unrestricted edge costs.
IEEE Transactions on Systems, Man, and Cybernetics, Part A 31(6): 497-507 (2001) |
1998 |
5 | EE | Parthasarathi Dasgupta,
Susmita Sur-Kolay,
Bhargab B. Bhattacharya:
A unified approach to topology generation and optimal sizing of floorplans.
IEEE Trans. on CAD of Integrated Circuits and Systems 17(2): 126-135 (1998) |
1997 |
4 | EE | Parthasarathi Dasgupta,
Susmita Sur-Kolay:
Slicibility of rectangular graphs and floorplan optimization.
ISPD 1997: 150-155 |
1996 |
3 | EE | Parthasarathi Dasgupta,
Anup K. Sen,
Subhas C. Nandy,
Bhargab B. Bhattacharya:
Geometric bipartitioning problem and its applications to VLSI.
VLSI Design 1996: 400-405 |
1995 |
2 | EE | Parthasarathi Dasgupta,
Susmita Sur-Kolay,
Bhargab B. Bhattacharya:
A unified approach to topology generation and area optimization of general floorplans.
ICCAD 1995: 712-715 |
1 | EE | P. S. Dasgupta,
Susmita Sur-Kolay,
Bhargab B. Bhattacharya:
VLSI floorplan generation and area optimization using AND-OR graph search.
VLSI Design 1995: 370-375 |