| 2007 |
|---|
| 4 | EE | Saibal Mukhopadhyay,
Keunwoo Kim,
Jae-Joon Kim,
Shih-Hsien Lo,
Rajiv V. Joshi,
Ching-Te Chuang,
Kaushik Roy:
Estimation of gate-to-channel tunneling current in ultra-thin oxide sub-50nm double gate devices.
Microelectronics Journal 38(8-9): 931-941 (2007) |
| 2006 |
|---|
| 3 | EE | Koushik K. Das,
Shih-Hsien Lo,
Ching-Te Chuang:
High Performance MTCMOS Technique for Leakage Reduction in Hybrid SOI-Epitaxial Technologies with Enhanced-Mobility PFET Header.
VLSI Design 2006: 758-761 |
| 2005 |
|---|
| 2 | EE | Saibal Mukhopadhyay,
Keunwoo Kim,
Jae-Joon Kim,
Shih-Hsien Lo,
Rajiv V. Joshi,
Ching-Te Chuang,
Kaushik Roy:
Modeling and Analysis of Gate Leakage in Ultra-thin Oxide Sub-50nm Double Gate Devices and Circuits.
ISQED 2005: 410-415 |
| 1999 |
|---|
| 1 | EE | Shih-Hsien Lo,
Douglas A. Buchanan,
Yuan Taur:
Modeling and characterization of quantization, polysilicon depletion, and direct tunneling effects in MOSFETs with ultrathin oxides.
IBM Journal of Research and Development 43(3): 327-338 (1999) |
