2009 | ||
---|---|---|
34 | EE | Pritha Banerjee, Megha Sangtani, Susmita Sur-Kolay: Floorplanning for Partial Reconfiguration in FPGAs. VLSI Design 2009: 125-130 |
33 | EE | Debasri Saha, Susmita Sur-Kolay: Encoding of Floorplans through Deterministic Perturbation. VLSI Design 2009: 315-320 |
32 | EE | Sriparna Saha, Susmita Sur-Kolay, Parthasarathi Dasgupta, Sanghamitra Bandyopadhyay: MAkE: Multiobjective algorithm for k-way equipartitioning of a point set. Appl. Soft Comput. 9(2): 711-724 (2009) |
2007 | ||
31 | EE | Debasri Saha, Parthasarathi Dasgupta, Susmita Sur-Kolay, Samar Sen-Sarma: A Novel Scheme for Encoding and Watermark Embedding in VLSI Physical Design for IP Protection. ICCTA 2007: 111-116 |
30 | EE | Pritha Banerjee, Susmita Sur-Kolay: Faster Placer for Island-Style FPGAs. ICCTA 2007: 117-121 |
29 | EE | Debasri Saha, Susmita Sur-Kolay: Fast Robust Intellectual Property Protection for VLSI Physical Design. ICIT 2007: 1-6 |
28 | EE | Pritha Banerjee, Susmita Sur-Kolay, Arijit Bishnu: Floorplanning in Modern FPGAs. VLSI Design 2007: 893-898 |
27 | EE | Subhashis Majumder, Susmita Sur-Kolay, Bhargab B. Bhattacharya, Swarup Kumar Das: Hierarchical partitioning of VLSI floorplans by staircases. ACM Trans. Design Autom. Electr. Syst. 12(1): (2007) |
2006 | ||
26 | EE | Sriparna Saha, Susmita Sur-Kolay, Sanghamitra Bandyopadhyay, Parthasarathi Dasgupta: Multiobjective Genetic Algorithm for k-way Equipartitioning of a Point Set with Application to CAD-VLSI. ICIT 2006: 281-284 |
25 | EE | Debasis Mitra, Subhasis Bhattacharjee, Susmita Sur-Kolay, Bhargab B. Bhattacharya, Sujit T. Zachariah, Sandip Kundu: Test Pattern Generation for Power Supply Droop Faults. VLSI Design 2006: 343-348 |
2005 | ||
24 | Pritha Banerjee, Subhasis Bhattacharjee, Susmita Sur-Kolay, Sandip Das, Subhas C. Nandy: Fast FPGA Placement using Space-filling Curve. FPL 2005: 415-420 | |
23 | EE | Susmita Sur-Kolay, Satyajit Banerjee, S. Mukhopadhyaya, C. A. Murthy: Genetic Algorithm for Double Digest Problem. PReMI 2005: 623-629 |
22 | EE | Subhashis Majumder, Susmita Sur-Kolay, Subhas C. Nandy, Bhargab B. Bhattacharya, B. Chakraborty: Hot Spots and Zones in a Chip: A Geometrician's View. VLSI Design 2005: 691-696 |
2004 | ||
21 | EE | Chandra Tirumurti, Sandip Kundu, Susmita Sur-Kolay, Yi-Shing Chang: A Modeling Approach for Addressing Power Supply Switching Noise Related Failures of Integrated Circuit. DATE 2004: 1078-1083 |
20 | EE | Sanjay Goswami, Susmita Sur-Kolay: Virtual Molecular Computing - Emulating DNA Molecules. IWDC 2004: 95-101 |
19 | EE | Susmita Sur-Kolay, Parthasarathi Dasgupta, Bhargab B. Bhattacharya, Sujit T. Zachariah: Physical Design Trends and Layout-Based Fault Modeling. VLSI Design 2004: 6-8 |
18 | EE | Sandip Das, Susmita Sur-Kolay, Bhargab B. Bhattacharya: Manhattan-diagonal routing in channels and switchboxes. ACM Trans. Design Autom. Electr. Syst. 9(1): 75-104 (2004) |
2003 | ||
17 | Susmita Sur-Kolay, Satyajit Banerjee, C. A. Murthy: Flavours of Traveling Salesman Problem in VLSI Design. IICAI 2003: 656-667 | |
2001 | ||
16 | EE | Subhashis Majumder, Susmita Sur-Kolay, Bhargab B. Bhattacharya, Subhas C. Nandy: Area(number)-balanced hierarchy of staircase channels with minimum crossing nets. ISCAS (5) 2001: 395-398 |
15 | Steven Derrien, Sanjay V. Rajopadhye, Susmita Sur-Kolay: Combined instruction and loop parallelism in array synthesis for FPGAs. ISSS 2001: 165-170 | |
14 | EE | Koushik Sinha, Susmita Sur-Kolay, Bhargab B. Bhattacharya, P. S. Dasgupta: Partitioning Routing Area into Zones with Distinct Pins. VLSI Design 2001: 345- |
13 | EE | Parthasarathi Dasgupta, Susmita Sur-Kolay: Slicible rectangular graphs and their optimal floorplans. ACM Trans. Design Autom. Electr. Syst. 6(4): 447-470 (2001) |
2000 | ||
12 | EE | Susmita Sur-Kolay, Marly Roncken, Ken S. Stevens, Parimal Pal Chaudhuri, Rob Roy: Fsimac: a fault simulator for asynchronous sequential circuits. Asian Test Symposium 2000: 114-119 |
11 | EE | Steven Derrien, Sanjay V. Rajopadhye, Susmita Sur-Kolay: Optimal Partitioning for FPGA Based Regular Array Implementations. PARELEC 2000: 155-159 |
10 | EE | Swarup Bhunia, Subhashis Majumder, Ayan Sircar, Susmita Sur-Kolay, Bhargab B. Bhattacharya: Topological Routing Amidst Polygonal Obstacles. VLSI Design 2000: 274-279 |
1998 | ||
9 | EE | Sandip Das, Susmita Sur-Kolay, Bhargab B. Bhattacharya: Routing of L-Shaped Channels, Switchboxes and Staircases in Manhattan-Diagonal Model. VLSI Design 1998: 65- |
8 | EE | Parthasarathi Dasgupta, Susmita Sur-Kolay, Bhargab B. Bhattacharya: A unified approach to topology generation and optimal sizing of floorplans. IEEE Trans. on CAD of Integrated Circuits and Systems 17(2): 126-135 (1998) |
1997 | ||
7 | EE | Parthasarathi Dasgupta, Susmita Sur-Kolay: Slicibility of rectangular graphs and floorplan optimization. ISPD 1997: 150-155 |
1995 | ||
6 | Abhik Roychoudhury, Susmita Sur-Kolay: Efficient Algorithms for Vertex Arboricity of Planar Graphs. FSTTCS 1995: 37-51 | |
5 | EE | Parthasarathi Dasgupta, Susmita Sur-Kolay, Bhargab B. Bhattacharya: A unified approach to topology generation and area optimization of general floorplans. ICCAD 1995: 712-715 |
4 | EE | P. S. Dasgupta, Susmita Sur-Kolay, Bhargab B. Bhattacharya: VLSI floorplan generation and area optimization using AND-OR graph search. VLSI Design 1995: 370-375 |
1992 | ||
3 | EE | Susmita Sur-Kolay, Bhargab B. Bhattacharya: Canonical Embedding of Rectangular Duals with Applications to VLSI Floorplanning. DAC 1992: 69-74 |
1991 | ||
2 | Susmita Sur-Kolay, Bhargab B. Bhattacharya: The Cycle Structure of Channel Graphs in Nonslicible Floorplans and A Unified Algorithm for Feasible Routing Order. ICCD 1991: 524-527 | |
1988 | ||
1 | Susmita Sur-Kolay, Bhargab B. Bhattacharya: Inherent Nonslicibility of Rectangular Duals in VLSI Floorplanning. FSTTCS 1988: 88-107 |