| 2008 |
|---|
| 13 | EE | Subhashis Majumder,
Bhargab B. Bhattacharya:
On the density and discrepancy of a 2D point set with applications to thermal analysis of VLSI chips.
Inf. Process. Lett. 107(5): 177-182 (2008) |
| 2007 |
|---|
| 12 | EE | Subhashis Majumder,
Susmita Sur-Kolay,
Bhargab B. Bhattacharya,
Swarup Kumar Das:
Hierarchical partitioning of VLSI floorplans by staircases.
ACM Trans. Design Autom. Electr. Syst. 12(1): (2007) |
| 2006 |
|---|
| 11 | EE | Subhashis Majumder,
Bhargab B. Bhattacharya:
Solving Thermal Problems of Hot Chips Using Voronoi Diagrams.
VLSI Design 2006: 545-548 |
| 2005 |
|---|
| 10 | EE | Subhashis Majumder,
Bhargab B. Bhattacharya:
Density or Discrepancy: A VLSI Designer's Dilemma in Hot Spot Analysis.
CCCG 2005: 167-170 |
| 9 | EE | Subhashis Majumder,
Susmita Sur-Kolay,
Subhas C. Nandy,
Bhargab B. Bhattacharya,
B. Chakraborty:
Hot Spots and Zones in a Chip: A Geometrician's View.
VLSI Design 2005: 691-696 |
| 2004 |
|---|
| 8 | EE | Subhashis Majumder,
Bhargab B. Bhattacharya,
Vishwani D. Agrawal,
Michael L. Bushnell:
A New Classification of Path-Delay Fault Testability in Terms of Stuck-at Faults.
J. Comput. Sci. Technol. 19(6): 955-964 (2004) |
| 7 | EE | Subhashis Majumder,
Subhas C. Nandy,
Bhargab B. Bhattacharya:
On Finding A Staircase Channel With Minimum Crossing Nets In A VLSI Floorplan.
Journal of Circuits, Systems, and Computers 13(5): 1019-1038 (2004) |
| 2001 |
|---|
| 6 | EE | Subhashis Majumder,
Susmita Sur-Kolay,
Bhargab B. Bhattacharya,
Subhas C. Nandy:
Area(number)-balanced hierarchy of staircase channels with minimum crossing nets.
ISCAS (5) 2001: 395-398 |
| 2000 |
|---|
| 5 | EE | Swarup Bhunia,
Subhashis Majumder,
Ayan Sircar,
Susmita Sur-Kolay,
Bhargab B. Bhattacharya:
Topological Routing Amidst Polygonal Obstacles.
VLSI Design 2000: 274-279 |
| 1999 |
|---|
| 4 | EE | Subhashis Majumder,
Bhargab B. Bhattacharya,
Vishwani D. Agrawal,
Michael L. Bushnell:
A Complete Characterization of Path Delay Faults through Stuck-at Faults.
VLSI Design 1999: 492-497 |
| 1998 |
|---|
| 3 | EE | Subhashis Majumder,
Michael L. Bushnell,
Vishwani D. Agrawal:
Path Delay Testing: Variable-Clock Versus Rated-Clock.
VLSI Design 1998: 470-475 |
| 2 | EE | Subhashis Majumder,
Subhas C. Nandy,
Bhargab B. Bhattacharya:
Partitioning VLSI Floorplans by Staircase Channels for Global Routing.
VLSI Design 1998: 59-64 |
| 1 | EE | Subhashis Majumder,
Vishwani D. Agrawal,
Michael L. Bushnell:
On Delay-Untestable Paths and Stuck-Fault Redundancy.
VTS 1998: 194-199 |
