Shabbir H. Batterywala

2009
14	EE	Subramanian Rajagopalan, Sambuddha Bhattacharya, Shabbir H. Batterywala: Efficient Analog/RF Layout Closure with Compaction Based Legalization. VLSI Design 2009: 137-142
2008
13	EE	Sambuddha Bhattacharya, Shabbir H. Batterywala, Subramanian Rajagopalan, Hi-Keung Tony Ma, Narendra V. Shenoy: On Efficient and Robust Constraint Generation for Practical Layout Legalization. ISQED 2008: 379-384
12	EE	Shabbir H. Batterywala, Sambuddha Bhattacharya, Subramanian Rajagopalan, Hi-Keung Tony Ma, Narendra V. Shenoy: Cell Swapping Based Migration Methodology for Analog and Custom Layouts. ISQED 2008: 450-455
2007
11	EE	Subramanian Rajagopalan, Shabbir H. Batterywala: A 3-dimensional FEM Based Resistance Extraction. VLSI Design 2007: 565-570
10	EE	Debjit Sinha, Jianfeng Luo, Subramanian Rajagopalan, Shabbir H. Batterywala, Narendra V. Shenoy, Hai Zhou: Impact of Modern Process Technologies on the Electrical Parameters of Interconnects. VLSI Design 2007: 875-880
2006
9	EE	Shabbir H. Batterywala, Rohit Ananthakrishna, Yansheng Luo, Alex Gyure: A Statistical Method for Fast and Accurate Capacitance Extraction in the Presence of Floating Dummy Fills. VLSI Design 2006: 129-134
8	EE	Rohit Ananthakrishna, Shabbir H. Batterywala: MoM - A Process Variation Aware Statistical Capacitance Extractor. VLSI Design 2006: 135-140
2005
7	EE	Shabbir H. Batterywala, Madhav P. Desai: Variance Reduction in Monte Carlo Capacitance Extraction. VLSI Design 2005: 85-90
2004
6	EE	Shabbir H. Batterywala, Narendra V. Shenoy: Computing Silent Gate Models for Noise Analysis from Slew and Delay Tables. VLSI Design 2004: 989-994
2003
5	EE	Shabbir H. Batterywala, Narendra V. Shenoy: A Method to Estimate Slew and Delay in Coupled Digital Circuits. VLSI Design 2003: 411-416
2002
4	EE	Shabbir H. Batterywala, Narendra V. Shenoy, William Nicholls, Hai Zhou: Track assignment: a desirable intermediate step between global routing and detailed routing. ICCAD 2002: 59-66
2001
3	EE	Shabbir H. Batterywala, H. Narayanan: Spectral Algorithm To Compute And Synthesize Reduced Order Passive Models For Arbitrary Rc Multiports. VLSI Design 2001: 500-
1999
2		Shabbir H. Batterywala, H. Narayanan: Efficient DC Analysis of RVJ Circuits for Moment and Derivative Commutations of Interconnect Networks. VLSI Design 1999: 169-174
1997
1	EE	Sachin B. Patkar, Shabbir H. Batterywala, M. Chandramouli, H. Narayanan: A New Partitioning Strategy Based on Supermodular Functions. VLSI Design 1997: 32-37

Coauthor Index

1	Rohit Ananthakrishna	[8] [9]
2	Sambuddha Bhattacharya	[12] [13] [14]
3	M. Chandramouli	[1]
4	Madhav P. Desai	[7]
5	Alex Gyure	[9]
6	Jianfeng Luo	[10]
7	Yansheng Luo	[9]
8	Hi-Keung Tony Ma	[12] [13]
9	H. Narayanan	[1] [2] [3]
10	William Nicholls	[4]
11	Sachin B. Patkar	[1]
12	Subramanian Rajagopalan	[10] [11] [12] [13] [14]
13	Narendra V. Shenoy	[4] [5] [6] [10] [12] [13]
14	Debjit Sinha	[10]
15	Hai Zhou	[4] [10]

Colors in the list of coauthors