Shabbir H. Batterywala

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14EESubramanian Rajagopalan, Sambuddha Bhattacharya, Shabbir H. Batterywala: Efficient Analog/RF Layout Closure with Compaction Based Legalization. VLSI Design 2009: 137-142
13EESambuddha Bhattacharya, Shabbir H. Batterywala, Subramanian Rajagopalan, Hi-Keung Tony Ma, Narendra V. Shenoy: On Efficient and Robust Constraint Generation for Practical Layout Legalization. ISQED 2008: 379-384
12EEShabbir H. Batterywala, Sambuddha Bhattacharya, Subramanian Rajagopalan, Hi-Keung Tony Ma, Narendra V. Shenoy: Cell Swapping Based Migration Methodology for Analog and Custom Layouts. ISQED 2008: 450-455
11EESubramanian Rajagopalan, Shabbir H. Batterywala: A 3-dimensional FEM Based Resistance Extraction. VLSI Design 2007: 565-570
10EEDebjit Sinha, Jianfeng Luo, Subramanian Rajagopalan, Shabbir H. Batterywala, Narendra V. Shenoy, Hai Zhou: Impact of Modern Process Technologies on the Electrical Parameters of Interconnects. VLSI Design 2007: 875-880
9EEShabbir H. Batterywala, Rohit Ananthakrishna, Yansheng Luo, Alex Gyure: A Statistical Method for Fast and Accurate Capacitance Extraction in the Presence of Floating Dummy Fills. VLSI Design 2006: 129-134
8EERohit Ananthakrishna, Shabbir H. Batterywala: MoM - A Process Variation Aware Statistical Capacitance Extractor. VLSI Design 2006: 135-140
7EEShabbir H. Batterywala, Madhav P. Desai: Variance Reduction in Monte Carlo Capacitance Extraction. VLSI Design 2005: 85-90
6EEShabbir H. Batterywala, Narendra V. Shenoy: Computing Silent Gate Models for Noise Analysis from Slew and Delay Tables. VLSI Design 2004: 989-994
5EEShabbir H. Batterywala, Narendra V. Shenoy: A Method to Estimate Slew and Delay in Coupled Digital Circuits. VLSI Design 2003: 411-416
4EEShabbir H. Batterywala, Narendra V. Shenoy, William Nicholls, Hai Zhou: Track assignment: a desirable intermediate step between global routing and detailed routing. ICCAD 2002: 59-66
3EEShabbir H. Batterywala, H. Narayanan: Spectral Algorithm To Compute And Synthesize Reduced Order Passive Models For Arbitrary Rc Multiports. VLSI Design 2001: 500-
2 Shabbir H. Batterywala, H. Narayanan: Efficient DC Analysis of RVJ Circuits for Moment and Derivative Commutations of Interconnect Networks. VLSI Design 1999: 169-174
1EESachin B. Patkar, Shabbir H. Batterywala, M. Chandramouli, H. Narayanan: A New Partitioning Strategy Based on Supermodular Functions. VLSI Design 1997: 32-37

Coauthor Index

1Rohit Ananthakrishna [8] [9]
2Sambuddha Bhattacharya [12] [13] [14]
3M. Chandramouli [1]
4Madhav P. Desai [7]
5Alex Gyure [9]
6Jianfeng Luo [10]
7Yansheng Luo [9]
8Hi-Keung Tony Ma [12] [13]
9H. Narayanan [1] [2] [3]
10William Nicholls [4]
11Sachin B. Patkar [1]
12Subramanian Rajagopalan [10] [11] [12] [13] [14]
13Narendra V. Shenoy [4] [5] [6] [10] [12] [13]
14Debjit Sinha [10]
15Hai Zhou [4] [10]

Colors in the list of coauthors

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)