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D. Vinay Kumar

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2006
2EEPalkesh Jain, D. Vinay Kumar, J. M. Vasi, Mahesh B. Patil: Evaluation of Non-Quasi-Static Effects during SEU in Deep-Submicron MOS Devices and Circuits. VLSI Design 2006: 188-193
2003
1EED. Vinay Kumar, Nihar R. Mohapatra, Mahesh B. Patil, V. Ramgopal Rao: Application of Look-up Table Approach to High-K Gate Dielectric MOS Transistor circuits. VLSI Design 2003: 128-

Coauthor Index

1Palkesh Jain [2]
2Nihar R. Mohapatra [1]
3Mahesh B. Patil [1] [2]
4V. Ramgopal Rao [1]
5J. M. Vasi [2]

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