| |
| 2006 | ||
|---|---|---|
| 2 | EE | Palkesh Jain, D. Vinay Kumar, J. M. Vasi, Mahesh B. Patil: Evaluation of Non-Quasi-Static Effects during SEU in Deep-Submicron MOS Devices and Circuits. VLSI Design 2006: 188-193 |
| 2003 | ||
| 1 | EE | D. Vinay Kumar, Nihar R. Mohapatra, Mahesh B. Patil, V. Ramgopal Rao: Application of Look-up Table Approach to High-K Gate Dielectric MOS Transistor circuits. VLSI Design 2003: 128- |
| 1 | Palkesh Jain | [2] |
| 2 | Nihar R. Mohapatra | [1] |
| 3 | Mahesh B. Patil | [1] [2] |
| 4 | V. Ramgopal Rao | [1] |
| 5 | J. M. Vasi | [2] |