2007 |
22 | EE | Sameer D. Sahasrabuddhe,
Hakim Raja,
Kavi Arya,
Madhav P. Desai:
AHIR: A Hardware Intermediate Representation for Hardware Generation from High-level Programs.
VLSI Design 2007: 245-250 |
21 | EE | G. Hazari,
Madhav P. Desai,
H. Kasture:
On the Impact of Address Space Assignment on Performance in Systems-on-Chip.
VLSI Design 2007: 540-545 |
20 | EE | Gaurav Trivedi,
Madhav P. Desai,
H. Narayanan:
Parallelization of DC Analysis through Multiport Decomposition.
VLSI Design 2007: 863-868 |
2006 |
19 | EE | Gaurav Trivedi,
Madhav P. Desai,
H. Narayanan:
Fast DC Analysis and Its Application to Combinatorial Optimization Problems.
VLSI Design 2006: 695-700 |
2005 |
18 | EE | Shabbir H. Batterywala,
Madhav P. Desai:
Variance Reduction in Monte Carlo Capacitance Extraction.
VLSI Design 2005: 85-90 |
17 | EE | Madhav P. Desai,
D. Manjunath:
On Range Matrices and Wireless Networks in d Dimensions.
WiOpt 2005: 190-196 |
2004 |
16 | EE | Vani Prasad,
Madhav P. Desai:
On Buffering Schemes for Long Multi-Layer Nets.
VLSI Design 2004: 455- |
15 | EE | G. Hazari,
Madhav P. Desai,
A. Gupta,
S. Chakraborty:
A Novel Technique Towards Eliminating the Global Clock in VLSI Circuits.
VLSI Design 2004: 565-570 |
14 | EE | Aditya Mittal,
Madhav P. Desai:
A Distributed and Pipelined Controller for a Modular and Scalable Hardware Emulator.
VLSI Design 2004: 571- |
2003 |
13 | EE | Vani Prasad,
Madhav P. Desai:
Interconnect Delay Minimization Using a Novel Pre-Mid-Post Buffer Strategy.
VLSI Design 2003: 417-422 |
12 | EE | Nihar R. Mohapatra,
Madhav P. Desai,
V. Ramgopal Rao:
Detailed Analysis of FIBL in MOS Transistors with High-K Gate Dielectrics.
VLSI Design 2003: 99-104 |
11 | EE | Madhav P. Desai,
H. Narayanan,
Sachin B. Patkar:
The realization of finite state machines by decomposition and the principal lattice of partitions of a submodular function.
Discrete Applied Mathematics 131(2): 299-310 (2003) |
2002 |
10 | EE | Maryam Shojaei Baghini,
Madhav P. Desai:
Impact of Technology Scaling on Metastability Performance of CMOS Synchronizing Latches.
VLSI Design 2002: 317- |
2001 |
9 | EE | Nihar R. Mohapatra,
A. Dutta,
Madhav P. Desai,
V. Ramgopal Rao:
Effect Of Fringing Capacitances In Sub 100 Nm Mosfet's With High-K Gate Dielectrics.
VLSI Design 2001: 479- |
8 | EE | Pratheep A. Nair,
Anubhav Gupta,
Madhav P. Desai:
An On-Chip Coupling Capacitance Measurement Technique.
VLSI Design 2001: 495-499 |
7 | EE | Nihar R. Mohapatra,
A. Dutta,
G. Sridhar,
Madhav P. Desai,
V. Ramgopal Rao:
Sub-100 nm CMOS circuit performance with high-K gate dielectrics.
Microelectronics Reliability 41(7): 1045-1048 (2001) |
2000 |
6 | EE | Jeegar Tilak Shah,
Madhav P. Desai,
Sugata Sanyal:
Inductance Characterization of Small Interconnects Using Test-Signal Method.
VLSI Design 2000: 376- |
1999 |
5 | EE | Rupesh S. Shelar,
Madhav P. Desai,
H. Narayanan:
Decomposition of Finite State Machines for Area, Delay Minimization.
ICCD 1999: 620-625 |
4 | EE | B. N. V. Malleswara Gupta,
H. Narayanan,
Madhav P. Desai:
A State Assignment Scheme Targeting Performance and Area.
VLSI Design 1999: 378-383 |
1998 |
3 | EE | Nevine Nassif,
Madhav P. Desai,
Dale H. Hall:
Robust Elmore Delay Models Suitable for Full Chip Timing Verification of a 600MHz CMOS Microprocessor.
DAC 1998: 230-235 |
1996 |
2 | EE | Madhav P. Desai,
Yao-Tsung Yen:
A Systematic Technique for Verifying Critical Path Delays in a 300MHz Alpha CPU Design Using Circuit Simulation.
DAC 1996: 125-130 |
1 | EE | Madhav P. Desai,
Radenko Cvijetic,
James Jensen:
Sizing of Clock Distribution Networks for High Performance CPU Chips.
DAC 1996: 389-394 |