| 2009 |
|---|
| 53 | EE | Sreehari Veeramachaneni,
A. Mahesh Kumar,
Venkat Tummala,
M. B. Srinivas:
Design of a Low Power, Variable-Resolution Flash ADC.
VLSI Design 2009: 117-122 |
| 52 | EE | Himanshu Thapliyal,
Hamid R. Arabnia,
M. B. Srinivas:
Efficient Reversible Logic Design of BCD Subtractors.
Transactions on Computational Science 3: 99-121 (2009) |
| 2008 |
|---|
| 51 | EE | J. V. R. Ravindra,
M. B. Srinivas:
Generic sub-space algorithm for generating reduced order models of linear time varying vlsi circuits.
ACM Great Lakes Symposium on VLSI 2008: 111-114 |
| 50 | EE | Chittarsu Raghunandan,
K. S. Sainarayanan,
M. B. Srinivas:
Process Variation Aware Bus-Coding Scheme for Delay Minimization in VLSI Interconnects.
ISQED 2008: 43-46 |
| 49 | EE | Lingamneni Avinash,
Kirthi Krishna Muntimadugu,
M. B. Srinivas:
A Novel Encoding Scheme for Delay and Energy Minimization in VLSI Interconnects with Built-In Error Detection.
ISVLSI 2008: 128-133 |
| 48 | EE | Vasanth Iyer,
Rammurthy Garimella,
M. B. Srinivas:
Training Data Compression Algorithms and Reliability in Large Wireless Sensor Networks.
SUTC 2008: 480-485 |
| 47 | EE | Sreehari Veeramachaneni,
Kirthi M. Krishna,
Prateek G. V.,
Subroto S.,
Bharat S.,
M. B. Srinivas:
A Novel Carry-Look Ahead Approach to a Unified BCD and Binary Adder/Subtractor.
VLSI Design 2008: 547-552 |
| 2007 |
|---|
| 46 | EE | Sreehari Veeramachaneni,
Lingamneni Avinash,
Kirthi M. Krishna,
M. B. Srinivas:
Novel architectures for efficient (m, n) parallel counters.
ACM Great Lakes Symposium on VLSI 2007: 188-191 |
| 45 | EE | Chittarsu Raghunandan,
K. S. Sainarayanan,
M. B. Srinivas:
Bus-encoding technique to reduce delay, power and simultaneous switching noise (SSN) in RLC interconnects.
ACM Great Lakes Symposium on VLSI 2007: 371-376 |
| 44 | EE | J. V. R. Ravindra,
M. B. Srinivas:
A Statistical Model for Estimating the Effect of Process Variations on Delay and Slew Metrics for VLSI Interconnects.
DSD 2007: 325-330 |
| 43 | EE | Keerthi Laal Kala,
M. B. Srinivas:
Rule Selection in Fuzzy Systems using Heuristics and Branch Prediction.
FOCI 2007: 603-607 |
| 42 | EE | Shashank Mittal,
Md. Zafar Ali Khan,
M. B. Srinivas:
Area Efficient High Speed Architecture of Bruun's FFT for Software Defined Radio.
GLOBECOM 2007: 3118-3122 |
| 41 | EE | Chittarsu Raghunandan,
K. S. Sainarayanan,
M. B. Srinivas:
Area Efficient Bus Encoding Technique for Minimizing Simultaneous Switching Noise (SSN).
ISCAS 2007: 1129-1132 |
| 40 | EE | Sreehari Veeramachaneni,
Kirthi M. Krishna,
Lingamneni Avinash,
Reddy Puppala Sreekanth,
M. B. Srinivas:
Novel High-Speed Redundant Binary to Binary converter using Prefix Networks.
ISCAS 2007: 3271-3274 |
| 39 | EE | Sreehari Veeramachaneni,
Kirthi M. Krishna,
Lingamneni Avinash,
Reddy Puppala Sreekanth,
M. B. Srinivas:
Novel, High-Speed 16-Digit BCD Adders Conforming to IEEE 754r Format.
ISVLSI 2007: 343-350 |
| 38 | EE | K. S. Sainarayanan,
Chittarsu Raghunandan,
M. B. Srinivas:
Delay and Power Minimization in VLSI Interconnects with Spatio-Temporal Bus-Encoding Scheme.
ISVLSI 2007: 401-408 |
| 37 | EE | Shashank Mittal,
Md. Zafar Ali Khan,
M. B. Srinivas:
A Comparative Study of Different FFT Architectures for Software Defined Radio.
SAMOS 2007: 375-384 |
| 36 | EE | Sudhakar Maddi,
M. B. Srinivas:
A unified and reconfigurable Montgomery Multiplier architecture without four-to-two CSA.
SBCCI 2007: 147-152 |
| 35 | EE | K. S. Sainarayanan,
Chittarsu Raghunandan,
M. B. Srinivas:
Bus encoding schemes for minimizing delay in VLSI interconnects.
SBCCI 2007: 184-189 |
| 34 | EE | Sreehari Veeramachaneni,
Kirthi M. Krishna,
Lingamneni Avinash,
Reddy Puppala Sreekanth,
M. B. Srinivas:
Novel Architectures for High-Speed and Low-Power 3-2, 4-2 and 5-2 Compressors.
VLSI Design 2007: 324-329 |
| 33 | EE | M. Sudhakar,
Ramachandruni Venkata Kamala,
M. B. Srinivas:
A Unified, Reconfigurable Architecture for Montgomery Multiplication in Finite Fields GF(p) and GF(2^n).
VLSI Design 2007: 750-755 |
| 32 | EE | M. Sudhakar,
Ramachandruni Venkata Kamala,
M. B. Srinivas:
A bit-sliced, scalable and unified montgomery multiplier architecture for RSA and ECC.
VLSI-SoC 2007: 252-257 |
| 31 | EE | J. V. R. Ravindra,
M. B. Srinivas:
Delay and Energy Efficient Coding Techniques for Capacitive Interconnects.
Journal of Circuits, Systems, and Computers 16(6): 929-942 (2007) |
| 30 | EE | M. Sudhakar,
Ramachandruni Venkata Kamala,
M. B. Srinivas:
New and Improved Architectures for Montgomery Modular Multiplication.
MONET 12(4): 281-291 (2007) |
| 2006 |
|---|
| 29 | EE | Keerthi Laal Kala,
M. B. Srinivas:
A Generic Architecture for Intelligent System Hardware.
APCCAS 2006: 321-326 |
| 28 | EE | Himanshu Thapliyal,
M. B. Srinivas:
The New BCD Subtractor and Its Reversible Logic Implementation.
Asia-Pacific Computer Systems Architecture Conference 2006: 466-472 |
| 27 | EE | K. S. Sainarayanan,
J. V. R. Ravindra,
M. B. Srinivas:
Minimizing Simultaneous Switching Noise (SSN) using Modified Odd/Even Bus Invert Method.
DELTA 2006: 336-339 |
| 26 | EE | Himanshu Thapliyal,
Anvesh Ramasahayam,
Vivek Reddy Kotha,
Kunul Gottimukkula,
M. B. Srinivas:
Modified Montgomery Modular Multiplication Using 4: 2 Compressor and CSA Adder.
DELTA 2006: 414-417 |
| 25 | EE | Ramachandruni Venkata Kamala,
M. Sudhakar,
M. B. Srinivas:
An Efficient Reconfigurable Montgomery Multiplier Architecture for GF(n).
DSD 2006: 155-159 |
| 24 | | Pallavi Devi Gopineedi,
Himanshu Thapliyal,
M. B. Srinivas,
Hamid R. Arabnia:
Novel and Efficient 4: 2 and 5: 2 Compressors with Minimum Number of Transistors Designed for Low-Power Operations.
ESA 2006: 160-168 |
| 23 | EE | K. S. Sainarayanan,
J. V. R. Ravindra,
M. B. Srinivas:
A novel, coupling driven, low power bus coding technique for minimizing capacitive crosstalk in VLSI interconnects.
ISCAS 2006 |
| 22 | EE | Himanshu Thapliyal,
Saurabh Kotiyal,
M. B. Srinivas:
Novel BCD Adders and Their Reversible Logic Implementation for IEEE 754r Format.
VLSI Design 2006: 387-392 |
| 21 | EE | Ramachandruni Venkata Kamala,
M. B. Srinivas:
High-Throughput Montgomery Modular Multiplication.
VLSI-SoC 2006: 58-62 |
| 20 | EE | Himanshu Thapliyal,
Saurabh Kotiyal,
M. B. Srinivas:
Novel BCD Adders and Their Reversible Logic Implementation for IEEE 754r Format
CoRR abs/cs/0603088: (2006) |
| 19 | EE | Himanshu Thapliyal,
M. B. Srinivas:
A New Reversible TSG Gate and Its Application For Designing Efficient Adder Circuits
CoRR abs/cs/0603091: (2006) |
| 18 | EE | Himanshu Thapliyal,
M. B. Srinivas:
An Extension to DNA Based Fredkin Gate Circuits: Design of Reversible Sequential Circuits using Fredkin Gates
CoRR abs/cs/0603092: (2006) |
| 17 | EE | Himanshu Thapliyal,
M. B. Srinivas:
Novel Reversible Multiplier Architecture Using Reversible TSG Gate
CoRR abs/cs/0605004: (2006) |
| 16 | EE | Himanshu Thapliyal,
M. B. Srinivas:
Novel Reversible TSG Gate and Its Application for Designing Components of Primitive Reversible/Quantum ALU
CoRR abs/cs/0609023: (2006) |
| 15 | EE | Himanshu Thapliyal,
M. B. Srinivas:
VLSI Implementation of RSA Encryption System Using Ancient Indian Vedic Mathematics
CoRR abs/cs/0609028: (2006) |
| 14 | EE | Himanshu Thapliyal,
Hamid R. Arabnia,
M. B. Srinivas:
Reduced Area Low Power High Throughput BCD Adders for IEEE 754r Format
CoRR abs/cs/0609036: (2006) |
| 2005 |
|---|
| 13 | | Himanshu Thapliyal,
M. B. Srinivas,
Hamid R. Arabnia:
Design And Analysis of A VLSI Based High Performance Low Power Parallel Square Architecture.
AMCS 2005: 72-76 |
| 12 | EE | Himanshu Thapliyal,
M. B. Srinivas:
A Novel Reversible TSG Gate and Its Application for Designing Reversible Carry Look-Ahead and Other Adder Architectures.
Asia-Pacific Computer Systems Architecture Conference 2005: 805-817 |
| 11 | | Himanshu Thapliyal,
M. B. Srinivas,
Hamid R. Arabnia:
Design for A Fast And Low Power 2's Complement Multiplier.
CDES 2005: 165-167 |
| 10 | | Himanshu Thapliyal,
M. B. Srinivas,
Rameshwar Rao,
Hamid R. Arabnia:
Verilog Coding Style for Efficient Synthesis In FPGA.
CDES 2005: 85-90 |
| 9 | | Saurabh Kotiyal,
Himanshu Thapliyal,
M. B. Srinivas,
Hamid R. Arabnia:
VLSI Implementation of O(n*n) Sorting Algorithms And Their Hardware Comparison.
CSC 2005: 74-77 |
| 8 | | K. S. Sainarayanan,
J. V. R. Ravindra,
M. B. Srinivas:
A novel deep submicron low power bus coding technique.
Circuits, Signals, and Systems 2005: 154-159 |
| 7 | | Himanshu Thapliyal,
M. B. Srinivas,
Hamid R. Arabnia:
A Reversible Version of 4 x 4 Bit Array Multiplier With Minimum Gates and Garbage Outputs.
ESA 2005: 106-116 |
| 6 | | Himanshu Thapliyal,
M. B. Srinivas,
Hamid R. Arabnia:
Reversible Logic Synthesis of Half, Full and Parallel Subtractors.
ESA 2005: 165-181 |
| 5 | | Himanshu Thapliyal,
M. B. Srinivas,
Hamid R. Arabnia:
A Need of Quantum Computing: Reversible Logic Synthesis of Parallel Binary Adder-Subtractor.
ESA 2005: 60-68 |
| 4 | EE | Keerthi Laal Kala,
M. B. Srinivas:
A 32-Bit Binary Floating Point Neuro-Chip.
ICNC (3) 2005: 1015-1021 |
| 3 | EE | Yaswanth Narvaneni,
M. B. Srinivas:
Local Language Support for Handheld Devices.
ITCC (2) 2005: 799-800 |
| 2 | | Himanshu Thapliyal,
M. B. Srinivas,
Hamid R. Arabnia:
Implementation of A Fast Square In RSA Encryption/Decryption Architecture.
Security and Management 2005: 371-374 |
| 1 | | Himanshu Thapliyal,
M. B. Srinivas,
Hamid R. Arabnia:
Faster RSA Encryption/Decryption Architecture Using an Efficient High Speed Overlay Multiplier.
Security and Management 2005: 40-44 |
