| 2008 |
|---|
| 7 | EE | Qiang Qiang,
Anna Nagurney:
A unified network performance measure with importance identification and the ranking of network components.
Optimization Letters 2(1): 127-142 (2008) |
| 2007 |
|---|
| 6 | EE | Jen-Chieh Ou,
Daniel G. Saab,
Qiang Qiang,
Jacob A. Abraham:
Reducing verification overhead with RTL slicing.
ACM Great Lakes Symposium on VLSI 2007: 399-404 |
| 2006 |
|---|
| 5 | EE | Qiang Qiang,
Daniel G. Saab,
Jacob A. Abraham:
Checking Nested Properties Using Bounded Model Checking and Sequential ATPG.
VLSI Design 2006: 225-230 |
| 2005 |
|---|
| 4 | EE | Shaolei Quan,
Qiang Qiang,
Chin-Long Wey:
Design of a CMOS Operational Amplifier for Extreme-Voltage Stress Test.
Asian Test Symposium 2005: 70-75 |
| 3 | | Qiang Qiang,
Daniel G. Saab,
Jacob A. Abraham:
An Emulation Model for Sequential ATPG-Based Bounded Model Checking.
FPL 2005: 469-474 |
| 2 | EE | Qiang Qiang,
Chia-Lun Chang,
Daniel G. Saab,
Jacob A. Abraham:
Case Study of ATPG-based Bounded Model Checking: Verifying USB2.0 IP Core.
ICCD 2005: 461-463 |
| 1 | EE | Shaolei Quan,
Qiang Qiang,
Chin-Long Wey:
A novel reconfigurable architecture of low-power unsigned multiplier for digital signal processing.
ISCAS (4) 2005: 3327-3330 |
