| |
| 2007 | ||
|---|---|---|
| 7 | EE | M. Jagadesh Kumar, Vivek Venkataraman, Susheel Nawal: Analytical Drain Current Model of Nanoscale Strained-Si/SiGe MOSFETs for Analog Circuit Simulation. VLSI Design 2007: 189-194 |
| 2006 | ||
| 6 | EE | M. Jagadesh Kumar, Ali A. Orouji: Phase Change Memory Faults. VLSI Design 2006: 108-112 |
| 2004 | ||
| 5 | EE | Anurag Chaudhry, M. Jagadesh Kumar: Exploring the Novel Characteristics of Fully Depleted Dual-Material Gate (DMG) SOI MOSFET using Two-Dimensional Numerical Simulation Studies. VLSI Design 2004: 662-665 |
| 4 | EE | M. Jagadesh Kumar, Vinod Parihar: A New Surface Accumulation Layer Transistor(SALTran) Concept for Current Gain Enhancement in Bipolar Transistors. VLSI Design 2004: 827-831 |
| 3 | EE | G. Venkateshwar Reddy, M. Jagadesh Kumar: Investigation of the novel attributes of a single-halo double gate SOI MOSFET: 2D simulation study. Microelectronics Journal 35(9): 761-765 (2004) |
| 2003 | ||
| 2 | EE | M. Jagadesh Kumar, D. Venkateshrao: A New Lateral SiGe-Base PNM Schottky Collector Bipolar Transistor on SOI for Non-saturating VLSI Logic Design. VLSI Design 2003: 489-492 |
| 1 | EE | M. Jagadesh Kumar, C. Linga Reddy: 2D-simulation and analysis of lateral SiC N-emitter SiGe P-base Schottky metal-collector (NPM) HBT on SOI. Microelectronics Reliability 43(7): 1145-1149 (2003) |
| 1 | Anurag Chaudhry | [5] |
| 2 | Susheel Nawal | [7] |
| 3 | Ali A. Orouji | [6] |
| 4 | Vinod Parihar | [4] |
| 5 | C. Linga Reddy | [1] |
| 6 | G. Venkateshwar Reddy | [3] |
| 7 | Vivek Venkataraman | [7] |
| 8 | D. Venkateshrao | [2] |