| |
| 2008 | ||
|---|---|---|
| 4 | EE | Deblina Sarkar, Deepanjan Datta, Sudeb Dasgupta: Modeling of Leakage Current Mechanisms in Nanoscale DG MOSFET and its Application to Low Power SRAM Design. JCP 3(2): 37-47 (2008) |
| 2007 | ||
| 3 | EE | Deblina Sarkar, Samiran Ganguly, Deepanjan Datta, A. Ananda Prasad Sarab, Sudeb Dasgupta: Modeling of Leakages in Nano-Scale DG MOSFET to Implement Low Power SRAM: A Device/Circuit Co-Design. VLSI Design 2007: 183-188 |
| 2006 | ||
| 2 | EE | Deepanjan Datta, Samiran Ganguly: Design of Multi-bit SET Adder and Its Fault Simulation. VLSI Design 2006: 549-552 |
| 1 | EE | Deepanjan Datta, A. Ananda Prasad Sarab, Sudeb Dasgupta: Two-dimensional numerical modeling of lightly doped nano-scale double-gate MOSFET. Microelectronics Journal 37(6): 537-545 (2006) |
| 1 | Sudeb Dasgupta | [1] [3] [4] |
| 2 | Samiran Ganguly | [2] [3] |
| 3 | A. Ananda Prasad Sarab | [1] [3] |
| 4 | Deblina Sarkar | [3] [4] |