2007 |
10 | EE | Yusuke Kobayashi,
C. Raghunathan Manoj,
Kazuo Tsutsui,
Venkanarayan Hariharan,
Kuniyuki Kakushima,
V. Ramgopal Rao,
Parhat Ahmet,
Hiroshi Iwai:
Parasitic Effects in Multi-Gate MOSFETs.
IEICE Transactions 90-C(10): 2051-2056 (2007) |
2006 |
9 | EE | K. Narasimhulu,
V. Ramgopal Rao:
Embedded Tutorial: Analog Circuit Performance Issues with Aggressively Scaled Gate Oxide CMOS Technologies.
VLSI Design 2006: 45-50 |
2004 |
8 | EE | K. Narasimhulu,
Siva Narendra,
V. Ramgopal Rao:
The Influence of Process Variations on the Halo MOSFETs and its Implications on the Analog Circuit performance.
VLSI Design 2004: 545-550 |
2003 |
7 | EE | Najeebuddin Hakim,
V. Ramgopal Rao,
J. Vasi:
Small Signal Characteristics of Thin Film Single Halo SOI MOSFET for Mixed Mode Applications.
VLSI Design 2003: 110-115 |
6 | EE | D. Vinay Kumar,
Nihar R. Mohapatra,
Mahesh B. Patil,
V. Ramgopal Rao:
Application of Look-up Table Approach to High-K Gate Dielectric MOS Transistor circuits.
VLSI Design 2003: 128- |
5 | EE | Abhisek Dixit,
V. Ramgopal Rao:
A Novel Dynamic Threshold Operation Using Electrically Induced Junction MOSFET in the Deep Sub-micrometer CMOS Regime.
VLSI Design 2003: 499-503 |
4 | EE | Nihar R. Mohapatra,
Madhav P. Desai,
V. Ramgopal Rao:
Detailed Analysis of FIBL in MOS Transistors with High-K Gate Dielectrics.
VLSI Design 2003: 99-104 |
2001 |
3 | EE | G. Shrivastav,
S. Mahapatra,
V. Ramgopal Rao,
J. Vasi,
K. G. Anil,
C. Fink,
Walter Hansch,
I. Eisele:
erformance Optimization Of 60 Nm Channel Length Vertical Mosfets Using Channel Engineering.
VLSI Design 2001: 475-478 |
2 | EE | Nihar R. Mohapatra,
A. Dutta,
Madhav P. Desai,
V. Ramgopal Rao:
Effect Of Fringing Capacitances In Sub 100 Nm Mosfet's With High-K Gate Dielectrics.
VLSI Design 2001: 479- |
1 | EE | Nihar R. Mohapatra,
A. Dutta,
G. Sridhar,
Madhav P. Desai,
V. Ramgopal Rao:
Sub-100 nm CMOS circuit performance with high-K gate dielectrics.
Microelectronics Reliability 41(7): 1045-1048 (2001) |