| |
| 2006 | ||
|---|---|---|
| 2 | EE | Shweta Chary, Michael L. Bushnell: Automatic Path-Delay Fault Test Generation for Combined Resistive Vias, Resistive Bridges, and Capacitive Crosstalk Delay Faults. VLSI Design 2006: 413-418 |
| 1 | EE | Shweta Chary, Michael L. Bushnell: Analog Macromodeling for Combined Resistive Vias, Resistive Bridges, and Capacitive Crosstalk Delay Faults. VLSI Design 2006: 818-823 |
| 1 | Michael L. Bushnell | [1] [2] |