| 2008 |
|---|
| 9 | EE | Reetuparna Das,
Asit K. Mishra,
Chrysostomos Nicopoulos,
Dongkook Park,
Vijay Narayanan,
Ravishankar Iyer,
Mazin S. Yousif,
Chita R. Das:
Performance and power optimization through data compression in Network-on-Chip architectures.
HPCA 2008: 215-225 |
| 8 | EE | Dongkook Park,
Soumya Eachempati,
Reetuparna Das,
Asit K. Mishra,
Yuan Xie,
Narayanan Vijaykrishnan,
Chita R. Das:
MIRA: A Multi-layered On-Chip Interconnect Router Architecture.
ISCA 2008: 251-261 |
| 2007 |
|---|
| 7 | EE | Jongman Kim,
Chrysostomos Nicopoulos,
Dongkook Park,
Reetuparna Das,
Yuan Xie,
Narayanan Vijaykrishnan,
Mazin S. Yousif,
Chita R. Das:
A novel dimensionally-decomposed router for on-chip communication in 3D architectures.
ISCA 2007: 138-149 |
| 2006 |
|---|
| 6 | EE | Dongkook Park,
Chrysostomos Nicopoulos,
Jongman Kim,
Narayanan Vijaykrishnan,
Chita R. Das:
Exploring Fault-Tolerant Network-on-Chip Architectures.
DSN 2006: 93-104 |
| 5 | EE | Jongman Kim,
Chrysostomos Nicopoulos,
Dongkook Park:
A Gracefully Degrading and Energy-Efficient Modular Router Architecture for On-Chip Networks.
ISCA 2006: 4-15 |
| 4 | EE | Chrysostomos Nicopoulos,
Dongkook Park,
Jongman Kim,
Narayanan Vijaykrishnan,
Mazin S. Yousif,
Chita R. Das:
ViChaR: A Dynamic Virtual Channel Regulator for Network-on-Chip Routers.
MICRO 2006: 333-346 |
| 3 | EE | Thomas D. Richardson,
Chrysostomos Nicopoulos,
Dongkook Park,
Narayanan Vijaykrishnan,
Yuan Xie,
Chita R. Das,
Vijay Degalahal:
A Hybrid SoC Interconnect with Dynamic TDMA-Based Transaction-Less Buses and On-Chip Networks.
VLSI Design 2006: 657-664 |
| 2005 |
|---|
| 2 | EE | Jongman Kim,
Dongkook Park,
Chrysostomos Nicopoulos,
Narayanan Vijaykrishnan,
Chita R. Das:
Design and analysis of an NoC architecture from performance, reliability and energy perspective.
ANCS 2005: 173-182 |
| 1 | EE | Jongman Kim,
Dongkook Park,
Theo Theocharides,
Narayanan Vijaykrishnan,
Chita R. Das:
A low latency router supporting adaptivity for on-chip interconnects.
DAC 2005: 559-564 |
