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Xin Jia

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2006
7EEXin Jia, Ranga Vemuri: Studying a GALS FPGA architecture using a parameterized automatic design flow. ICCAD 2006: 688-693
6EEXin Jia, Ranga Vemuri: CAD Tools for a Globally Asynchronous Locally Synchronous FPGA Architecture. VLSI Design 2006: 251-256
2005
5EEXin Jia, Ranga Vemuri: Using GALS architecture to reduce the impact of long wire delay on FPGA performance. ASP-DAC 2005: 1260-1263
4EEXin Jia, Ranga Vemuri: The GAPLA: A Globally Asynchronous Locally Synchronous FPGA Architecture. FCCM 2005: 291-292
3 Xin Jia, Ranga Vemuri: A Novel Asynchronous FPGA Architecture Design and Its Performance Evaluation. FPL 2005: 287-292
2004
2 Xin Jia, Ranga Vemuri: A Design Methodology for Self-Timed Event Logic Pipelines. ESA/VLSI 2004: 475-479
1EEXin Jia, Jayanthi Rajagopalan, Ranga Vemuri: A Dynamically Reconfigurable Asynchronous FPGA Architecture. FPL 2004: 836-841

Coauthor Index

1Jayanthi Rajagopalan [1]
2Ranga Vemuri [1] [2] [3] [4] [5] [6] [7]

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)