2007 |
22 | EE | Deepak C. Sekar,
Azad Naeemi,
Reza Sarvari,
Jeffrey A. Davis,
James D. Meindl:
IntSim: A CAD tool for optimization of multilevel interconnect networks.
ICCAD 2007: 560-567 |
21 | EE | Ajay Joshi,
Gerald G. Lopez,
Jeffrey A. Davis:
Design and Optimization of On-Chip Interconnects Using Wave-Pipelined Multiplexed Routing.
IEEE Trans. VLSI Syst. 15(9): 990-1002 (2007) |
2006 |
20 | EE | Pranav Anbalagan,
Jeffrey A. Davis:
A priori prediction of tightly clustered connections based on heuristic classification trees.
SLIP 2006: 9-15 |
19 | EE | Ajay Joshi,
Vinita V. Deodhar,
Jeffrey A. Davis:
Low Power Multilevel Interconnect Networks Using Wave-Pipelined Multiplexed (WPM) Routing.
VLSI Design 2006: 773-776 |
2005 |
18 | EE | Ajay Joshi,
Jeffrey A. Davis:
Wave-pipelined 2-slot time division multiplexed (WP/2-TDM) routing.
ACM Great Lakes Symposium on VLSI 2005: 446-451 |
17 | EE | Vinita V. Deodhar,
Jeffrey A. Davis:
Voltage Scaling, Wire Sizing and Repeater Insertion Design Rules for Wave-Pipelined VLSI Global Interconnect Circuits.
ISQED 2005: 592-597 |
16 | EE | Vinita V. Deodhar,
Jeffrey A. Davis:
Optimization of throughput performance for low-power VLSI interconnects.
IEEE Trans. VLSI Syst. 13(3): 308-318 (2005) |
15 | EE | Ajay Joshi,
Jeffrey A. Davis:
Wave-pipelined multiplexed (WPM) routing for gigascale integration (GSI).
IEEE Trans. VLSI Syst. 13(8): 899-910 (2005) |
2004 |
14 | EE | Ajay Joshi,
Jeffrey A. Davis:
A 2-slot time-division multiplexing (TDM) interconnect network for gigascale integration (GSI).
SLIP 2004: 64-68 |
13 | EE | Pranav Anbalagan,
Jeffrey A. Davis:
Maximum Multiplicity Distributions for Length Prediction Driven Placement.
VLSI Design 2004: 981- |
2003 |
12 | EE | Vinita V. Deodhar,
Jeffrey A. Davis:
Voltage scaling and repeater insertion for high-throughput low-power interconnects.
ISCAS (5) 2003: 349-352 |
11 | EE | Pranav Anbalagan,
Jeffrey A. Davis:
Maximum multiplicity distributions (MMD).
SLIP 2003: 107-113 |
2002 |
10 | EE | Raguraman Venkatesan,
Jeffrey A. Davis,
James D. Meindl:
A physical model for the transient response of capacitively loaded distributed rlc interconnects.
DAC 2002: 763-766 |
9 | EE | James D. Meindl,
Jeffrey A. Davis,
Payman Zarkesh-Ha,
Chirag S. Patel,
Kevin P. Martin,
Paul A. Kohl:
Interconnect opportunities for gigascale integration.
IBM Journal of Research and Development 46(2-3): 245-264 (2002) |
2001 |
8 | EE | Raguraman Venkatesan,
Jeffrey A. Davis,
Keith A. Bowman,
James D. Meindl:
Optimal n-tier multilevel interconnect architectures for gigascale integration (GSI).
IEEE Trans. VLSI Syst. 9(6): 899-912 (2001) |
7 | EE | James W. Joyner,
Raguraman Venkatesan,
Payman Zarkesh-Ha,
Jeffrey A. Davis,
James D. Meindl:
Impact of three-dimensional architectures on interconnects in gigascale integration.
IEEE Trans. VLSI Syst. 9(6): 922-928 (2001) |
2000 |
6 | EE | Raguraman Venkatesan,
Jeffrey A. Davis,
Keith A. Bowman,
James D. Meindl:
Minimum power and area n-tier multilevel interconnect architectures using optimal repeater insertion.
ISLPED 2000: 167-172 |
5 | EE | Payman Zarkesh-Ha,
Jeffrey A. Davis,
William Loh,
James D. Meindl:
Prediction of interconnect fan-out distribution using Rent's rule.
SLIP 2000: 107-112 |
4 | EE | James W. Joyner,
Payman Zarkesh-Ha,
Jeffrey A. Davis,
James D. Meindl:
Vertical pitch limitations on performance enhancement in bonded three-dimensional interconnect architectures.
SLIP 2000: 123-127 |
3 | EE | Jeffrey A. Davis,
Raguraman Venkatesan,
Keith A. Bowman,
James D. Meindl:
Gigascale integration (GSI) interconnect limits and n-tier multilevel interconnect architectural solutions (discussion session).
SLIP 2000: 147-148 |
2 | EE | Payman Zarkesh-Ha,
Jeffrey A. Davis,
James D. Meindl:
Prediction of net-length distribution for global interconnects in a heterogeneous system-on-a-chip.
IEEE Trans. VLSI Syst. 8(6): 649-659 (2000) |
1 | EE | Qiang Chen,
Jeffrey A. Davis,
Payman Zarkesh-Ha,
James D. Meindl:
A compact physical via blockage model.
IEEE Trans. VLSI Syst. 8(6): 689-692 (2000) |