Himanshu Thapliyal

2009
42	EE	Himanshu Thapliyal, Nagarajan Ranganathan: Conservative QCA Gate (CQCA) for Designing Concurrently Testable Molecular QCA Circuits. VLSI Design 2009: 511-516
41	EE	Himanshu Thapliyal, Hamid R. Arabnia, M. B. Srinivas: Efficient Reversible Logic Design of BCD Subtractors. Transactions on Computational Science 3: 99-121 (2009)
2007
40		Himanshu Thapliyal, Hamid R. Arabnia, Rajnish Bajpai, Kamal K. Sharma: Partial Reversible Gates(PRG) for Reversible BCD Arithmetic. CDES 2007: 90-94
39	EE	Himanshu Thapliyal, A. Prasad Vinod: Designing Efficient Online Testable Reversible Adders With New Reversible Gate. ISCAS 2007: 1085-1088
38	EE	Himanshu Thapliyal, A. Prasad Vinod: Design of Reversible Sequential Elements With Feasibility of Transistor Implementation. ISCAS 2007: 625-628
37		Himanshu Thapliyal, Hamid R. Arabnia, Rajnish Bajpai, Kamal K. Sharma: Combined Integer and Variable Precision (CIVP) Floating Point Multiplication Architecture for FPGAs. PDPTA 2007: 449-452
36	EE	Himanshu Thapliyal, Hamid R. Arabnia, Rajnish Bajpai, Kamal K. Sharma: Combined Integer and Variable Precision (CIVP) Floating Point Multiplication Architecture for FPGAs CoRR abs/0711.2671: (2007)
35	EE	Himanshu Thapliyal, Hamid R. Arabnia, Rajnish Bajpai, Kamal K. Sharma: Partial Reversible Gates(PRG) for Reversible BCD Arithmetic CoRR abs/0711.2674: (2007)
2006
34	EE	Himanshu Thapliyal, A. Prasad Vinod: Transistor Realization of Reversible TSG Gate and Reversible Adder Architectures. APCCAS 2006: 418-421
33	EE	Himanshu Thapliyal, M. B. Srinivas: The New BCD Subtractor and Its Reversible Logic Implementation. Asia-Pacific Computer Systems Architecture Conference 2006: 466-472
32		Himanshu Thapliyal, A. Rameshwar, Rajnish Bajpai, Hamid R. Arabnia: Novel NAND and AND Gate Using DNA Ligation and Two Transistors Implementations. CDES 2006: 130-134
31		Himanshu Thapliyal, Vishal Verma, Hamid R. Arabnia: A Double Precision Floating Point Multiplier Suitably Designed for FPGAs and ASICs. CDES 2006: 36-38
30		Himanshu Thapliyal, Hamid R. Arabnia: Modified Carry Look Ahead BCD Adder With CMOS and Reversible Logic Implementation. CDES 2006: 64-69
29		Himanshu Thapliyal, Hamid R. Arabnia: A Reversible Programmable Logic Array (RPLA) Using Fredkin and Feynman Gates for Industrial Electronics and Applications. CDES 2006: 70-76
28	EE	Himanshu Thapliyal, Anvesh Ramasahayam, Vivek Reddy Kotha, Kunul Gottimukkula, M. B. Srinivas: Modified Montgomery Modular Multiplication Using 4: 2 Compressor and CSA Adder. DELTA 2006: 414-417
27		Pallavi Devi Gopineedi, Himanshu Thapliyal, M. B. Srinivas, Hamid R. Arabnia: Novel and Efficient 4: 2 and 5: 2 Compressors with Minimum Number of Transistors Designed for Low-Power Operations. ESA 2006: 160-168
26	EE	Himanshu Thapliyal, Sumedha K. Gupta: Design of Novel Reversible Carry Look-Ahead BCD Subtractor. ICIT 2006: 253-258
25	EE	Himanshu Thapliyal, Saurabh Kotiyal, M. B. Srinivas: Novel BCD Adders and Their Reversible Logic Implementation for IEEE 754r Format. VLSI Design 2006: 387-392
24	EE	Himanshu Thapliyal, Saurabh Kotiyal, M. B. Srinivas: Novel BCD Adders and Their Reversible Logic Implementation for IEEE 754r Format CoRR abs/cs/0603088: (2006)
23	EE	Himanshu Thapliyal, M. B. Srinivas: A New Reversible TSG Gate and Its Application For Designing Efficient Adder Circuits CoRR abs/cs/0603091: (2006)
22	EE	Himanshu Thapliyal, M. B. Srinivas: An Extension to DNA Based Fredkin Gate Circuits: Design of Reversible Sequential Circuits using Fredkin Gates CoRR abs/cs/0603092: (2006)
21	EE	Himanshu Thapliyal, M. B. Srinivas: Novel Reversible Multiplier Architecture Using Reversible TSG Gate CoRR abs/cs/0605004: (2006)
20	EE	Himanshu Thapliyal, M. B. Srinivas: Novel Reversible TSG Gate and Its Application for Designing Components of Primitive Reversible/Quantum ALU CoRR abs/cs/0609023: (2006)
19	EE	Himanshu Thapliyal, M. B. Srinivas: VLSI Implementation of RSA Encryption System Using Ancient Indian Vedic Mathematics CoRR abs/cs/0609028: (2006)
18	EE	Himanshu Thapliyal, Hamid R. Arabnia: Reversible Programmable Logic Array (RPLA) using Fredkin & Feynman Gates for Industrial Electronics and Applications CoRR abs/cs/0609029: (2006)
17	EE	Himanshu Thapliyal, Hamid R. Arabnia, M. B. Srinivas: Reduced Area Low Power High Throughput BCD Adders for IEEE 754r Format CoRR abs/cs/0609036: (2006)
16	EE	Himanshu Thapliyal, Mark Zwolinski: Reversible Logic to Cryptographic Hardware: A New Paradigm CoRR abs/cs/0610089: (2006)
15	EE	Himanshu Thapliyal, Hamid R. Arabnia, A. Prasad Vinod: Combined Integer and Floating Point Multiplication Architecture(CIFM) for FPGAs and Its Reversible Logic Implementation CoRR abs/cs/0610090: (2006)
2005
14		Himanshu Thapliyal, M. B. Srinivas, Hamid R. Arabnia: Design And Analysis of A VLSI Based High Performance Low Power Parallel Square Architecture. AMCS 2005: 72-76
13	EE	Himanshu Thapliyal, M. B. Srinivas: A Novel Reversible TSG Gate and Its Application for Designing Reversible Carry Look-Ahead and Other Adder Architectures. Asia-Pacific Computer Systems Architecture Conference 2005: 805-817
12		Himanshu Thapliyal, M. B. Srinivas, Hamid R. Arabnia: Design for A Fast And Low Power 2's Complement Multiplier. CDES 2005: 165-167
11		Himanshu Thapliyal, M. B. Srinivas, Rameshwar Rao, Hamid R. Arabnia: Verilog Coding Style for Efficient Synthesis In FPGA. CDES 2005: 85-90
10		Saurabh Kotiyal, Himanshu Thapliyal, M. B. Srinivas, Hamid R. Arabnia: VLSI Implementation of O(n*n) Sorting Algorithms And Their Hardware Comparison. CSC 2005: 74-77
9		Himanshu Thapliyal, M. B. Srinivas, Hamid R. Arabnia: A Reversible Version of 4 x 4 Bit Array Multiplier With Minimum Gates and Garbage Outputs. ESA 2005: 106-116
8		Himanshu Thapliyal, M. B. Srinivas, Hamid R. Arabnia: Reversible Logic Synthesis of Half, Full and Parallel Subtractors. ESA 2005: 165-181
7		Himanshu Thapliyal, M. B. Srinivas, Hamid R. Arabnia: A Need of Quantum Computing: Reversible Logic Synthesis of Parallel Binary Adder-Subtractor. ESA 2005: 60-68
6		Himanshu Thapliyal, M. B. Srinivas, Hamid R. Arabnia: Implementation of A Fast Square In RSA Encryption/Decryption Architecture. Security and Management 2005: 371-374
5		Himanshu Thapliyal, M. B. Srinivas, Hamid R. Arabnia: Faster RSA Encryption/Decryption Architecture Using an Efficient High Speed Overlay Multiplier. Security and Management 2005: 40-44
2004
4		Himanshu Thapliyal, Hamid R. Arabnia: High Speed Efficient N Bit by N Bit Division Algorithm and Architecture Based on Ancient Indian Vedic Mathematics. ESA/VLSI 2004: 413-416
3		Himanshu Thapliyal, Hamid R. Arabnia: A Time-Area-Power Efficient Multiplier and Square Architecture Based on Ancient Indian Vedic Mathematics. ESA/VLSI 2004: 434-439
2		Himanshu Thapliyal, Hamid R. Arabnia: A Novel Parallel Multiply and Accumulate (V-MAC) Architecture Based on Ancient Indian Vedic Mathematics. ESA/VLSI 2004: 440-446
2003
1		Vishal Verma, Himanshu Thapliyal: A High Speed Efficient N x N Bit Multiplier Based on Ancient Indian Vedic Mathematics. VLSI 2003: 361-365

Coauthor Index

1	Hamid R. Arabnia	[2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [14] [15] [17] [18] [27] [29] [30] [31] [32] [35] [36] [37] [40] [41]
2	Rajnish Bajpai	[32] [35] [36] [37] [40]
3	Pallavi Devi Gopineedi	[27]
4	Kunul Gottimukkula	[28]
5	Sumedha K. Gupta	[26]
6	Vivek Reddy Kotha	[28]
7	Saurabh Kotiyal	[10] [24] [25]
8	Anvesh Ramasahayam	[28]
9	A. Rameshwar	[32]
10	N. Ranganathan (Nagarajan Ranganathan)	[42]
11	Rameshwar Rao	[11]
12	Kamal K. Sharma	[35] [36] [37] [40]
13	M. B. Srinivas	[5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [17] [19] [20] [21] [22] [23] [24] [25] [27] [28] [33] [41]
14	Vishal Verma	[1] [31]
15	A. Prasad Vinod	[15] [34] [38] [39]
16	Mark Zwolinski	[16]

Colors in the list of coauthors