Aswath Oruganti
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2006
1
EE
Aswath Oruganti,
Nagarajan Ranganathan
: Leakage Power Reduction in Dual-Vdd and Dual-Vth Designs through Probabilistic Analysis of Vth Variation.
VLSI Design 2006
: 766-769
Coauthor
Index
1
N. Ranganathan
(Nagarajan Ranganathan)
[
1
]
Copyright ©
Sun May 17 03:24:02 2009 by
Michael Ley
(
ley@uni-trier.de
)
