2007 |
11 | EE | Taylan Yemliha,
Guangyu Chen,
Ozcan Ozturk,
Mahmut T. Kandemir,
Vijay Degalahal:
Compiler-Directed Code Restructuring for Operating with Compressed Arrays.
VLSI Design 2007: 221-226 |
10 | EE | Mahmut T. Kandemir,
Ozcan Ozturk,
Vijay Degalahal:
Enhancing Locality in Two-Dimensional Space through Integrated Computation and Data Mappings.
VLSI Design 2007: 227-232 |
2006 |
9 | EE | Thomas D. Richardson,
Chrysostomos Nicopoulos,
Dongkook Park,
Narayanan Vijaykrishnan,
Yuan Xie,
Chita R. Das,
Vijay Degalahal:
A Hybrid SoC Interconnect with Dynamic TDMA-Based Transaction-Less Buses and On-Chip Networks.
VLSI Design 2006: 657-664 |
2005 |
8 | EE | Vijay Degalahal,
Tim Tuan:
Methodology for high level estimation of FPGA power consumption.
ASP-DAC 2005: 657-660 |
7 | EE | Jie S. Hu,
Feihui Li,
Vijay Degalahal,
Mahmut T. Kandemir,
Narayanan Vijaykrishnan,
Mary Jane Irwin:
Compiler-Directed Instruction Duplication for Soft Error Detection.
DATE 2005: 1056-1057 |
6 | EE | Vijay Degalahal,
Lin Li,
Narayanan Vijaykrishnan,
Mahmut T. Kandemir,
Mary Jane Irwin:
Soft errors issues in low-power caches.
IEEE Trans. VLSI Syst. 13(10): 1157-1166 (2005) |
2004 |
5 | EE | Lin Li,
Vijay Degalahal,
Narayanan Vijaykrishnan,
Mahmut T. Kandemir,
Mary Jane Irwin:
Soft error and energy consumption interactions: a data cache perspective.
ISLPED 2004: 132-137 |
4 | EE | Vijay Degalahal,
R. Ramanarayanan,
Narayanan Vijaykrishnan,
Yuan Xie,
Mary Jane Irwin:
The Effect of Threshold Voltages on the Soft Error Rate.
ISQED 2004: 503-508 |
3 | EE | Wei Zhang,
Jie S. Hu,
Vijay Degalahal,
Mahmut T. Kandemir,
Narayanan Vijaykrishnan,
Mary Jane Irwin:
Reducing instruction cache energy consumption using a compiler-based strategy.
TACO 1(1): 3-33 (2004) |
2003 |
2 | EE | Vijay Degalahal,
Narayanan Vijaykrishnan,
Mary Jane Irwin:
Analyzing Soft Errors in Leakage Optimized SRAM Design.
VLSI Design 2003: 227-233 |
2002 |
1 | EE | Wei Zhang,
Jie S. Hu,
Vijay Degalahal,
Mahmut T. Kandemir,
Narayanan Vijaykrishnan,
Mary Jane Irwin:
Compiler-directed instruction cache leakage optimization.
MICRO 2002: 208-218 |