| 2007 |
|---|
| 9 | EE | Narender Hanchate,
Nagarajan Ranganathan:
Integrated Gate and Wire Sizing at Post Layout Level.
ISVLSI 2007: 225-232 |
| 8 | EE | Narender Hanchate,
Nagarajan Ranganathan:
Statistical Gate Sizing for Yield Enhancement at Post Layout Level.
ISVLSI 2007: 245-252 |
| 2006 |
|---|
| 7 | EE | Narender Hanchate,
Nagarajan Ranganathan:
Post-Layout Gate Sizing for Interconnect Delay and Crosstalk Noise Optimization.
ISQED 2006: 92-97 |
| 6 | EE | Nagarajan Ranganathan,
Ravi Namballa,
Narender Hanchate:
CHESS: A Comprehensive Tool for CDFG Extraction and Synthesis of Low Power Designs from VHDL.
ISVLSI 2006: 329-334 |
| 5 | EE | Narender Hanchate,
Nagarajan Ranganathan:
A Linear Time Algorithm for Wire Sizing with Simultaneous Optimization of Interconnect Delay and Crosstalk Noise.
VLSI Design 2006: 283-290 |
| 4 | EE | Narender Hanchate,
Nagarajan Ranganathan:
A game-theoretic framework for multimetric optimization of interconnect delay, power, and crosstalk noise during wire sizing.
ACM Trans. Design Autom. Electr. Syst. 11(3): 711-739 (2006) |
| 3 | EE | Narender Hanchate,
Nagarajan Ranganathan:
Simultaneous Interconnect Delay and Crosstalk Noise Optimization through Gate Sizing Using Game Theory.
IEEE Trans. Computers 55(8): 1011-1023 (2006) |
| 2004 |
|---|
| 2 | EE | Narender Hanchate,
Nagarajan Ranganathan:
A New Technique for Leakage Reduction in CMOS Circuits using Self-Controlled Stacked Transistors.
VLSI Design 2004: 228-233 |
| 1 | | Narender Hanchate,
Nagarajan Ranganathan:
LECTOR: a technique for leakage reduction in CMOS circuits.
IEEE Trans. VLSI Syst. 12(2): 196-205 (2004) |
