dblp.uni-trier.dewww.uni-trier.de

Vikram Chandrasekhar

List of publications from the DBLP Bibliography Server - FAQ
Coauthor Index - Ask others: ACM DL/Guide - CiteSeer - CSB - Google - MSN - Yahoo

2009
17EEVikram Chandrasekhar, Marios Kountouris, Jeffrey G. Andrews: Coverage in Multi-Antenna Two-Tier Networks CoRR abs/0902.3210: (2009)
2008
16EEVikram Chandrasekhar, Jeffrey G. Andrews, Alan Gatherer: Femtocell Networks: A Survey CoRR abs/0803.0952: (2008)
15EEVikram Chandrasekhar, Jeffrey G. Andrews: Spectrum Allocation in Two-Tier Networks CoRR abs/0805.1226: (2008)
14EEVikram Chandrasekhar, Jeffrey G. Andrews, Tarik Muharemovic, Zukang Shen, Alan Gatherer: Power Control in Two-Tier Femtocell Networks CoRR abs/0810.3869: (2008)
13EEVikram Chandrasekhar, Frank Livingston, Joseph R. Cavallaro: Reducing dynamic power consumption in next generation DS-CDMA mobile communication receivers. IJES 3(3): 128-140 (2008)
2007
12EEVikram Chandrasekhar, Jeffrey G. Andrews: Uplink Capacity and Interference Avoidance for Two-Tier Cellular Networks. GLOBECOM 2007: 3322-3326
11EEWilliam Thies, Vikram Chandrasekhar, Saman P. Amarasinghe: A Practical Approach to Exploiting Coarse-Grained Pipeline Parallelism in C Programs. MICRO 2007: 356-369
10EEVikram Chandrasekhar, Jeffrey G. Andrews: Uplink Capacity and Interference Avoidance for Two-Tier Femtocell Networks CoRR abs/cs/0702132: (2007)
2006
9EEVivek Garg, Vikram Chandrasekhar, Milagros Sashikánth, V. Kamakoti: An Area and Configuration-Bit Optimized CLB Architecture and Timing-Driven Packing for FPGAs. VLSI Design 2006: 507-510
2005
8EEE. Syam Sundar Reddy, Vikram Chandrasekhar, Milagros Sashikánth, V. Kamakoti, Narayanan Vijaykrishnan: Cluster-based detection of SEU-caused errors in LUTs of SRAM-based FPGAs. ASP-DAC 2005: 1200-1203
7EEVivek Garg, Vikram Chandrasekhar, Milagros Sashikánth, V. Kamakoti: A novel CLB architecture and circuit packing algorithm for logic-area reduction in SRAM-based FPGAs. ASP-DAC 2005: 791-794
6EEVivek Garg, Vikram Chandrasekhar, Milagros Sashikánth, V. Kamakoti: A function generator-based reconfigurable system. ASP-DAC 2005: 905-909
5EEE. Syam Sundar Reddy, Vikram Chandrasekhar, Milagros Sashikánth, V. Kamakoti, Narayanan Vijaykrishnan: Efficient methodology for detection and correction of SEU-based interconnect errors in FPGAs using partial reconfiguration (abstract only). FPGA 2005: 265
4EEE. Syam Sundar Reddy, Vikram Chandrasekhar, Milagros Sashikánth, V. Kamakoti, Narayanan Vijaykrishnan: Online Detection and Diagnosis of Multiple Configuration Upsets in LUTs of SRAM-Based FPGAs. IPDPS 2005
3EEE. Syam Sundar Reddy, Vikram Chandrasekhar, Milagros Sashikánth, V. Kamakoti, Narayanan Vijaykrishnan: Detecting SEU-Caused Routing Errors in SRAM-Based FPGAs. VLSI Design 2005: 736-741
2003
2EEVikram Chandrasekhar, Frank Livingston, Joseph R. Cavallaro: Reducing dynamic power consumption in next generation DS-CDMA mobile communication receivers. ASAP 2003: 260-270
2002
1EEFrank Livingston, Vikram Chandrasekhar, M. Vaya, Joseph R. Cavallaro: Handset detector architectures for DS-CDMA wireless systems. ISCAS (3) 2002: 265-268

Coauthor Index

1Saman P. Amarasinghe [11]
2Jeffrey G. Andrews [10] [12] [14] [15] [16] [17]
3Joseph R. Cavallaro [1] [2] [13]
4Vivek Garg [6] [7] [9]
5Alan Gatherer [14] [16]
6V. Kamakoti [3] [4] [5] [6] [7] [8] [9]
7Marios Kountouris [17]
8Frank Livingston [1] [2] [13]
9Tarik Muharemovic [14]
10E. Syam Sundar Reddy [3] [4] [5] [8]
11Milagros Sashikánth [3] [4] [5] [6] [7] [8] [9]
12Zukang Shen [14]
13William Thies [11]
14M. Vaya [1]
15Narayanan Vijaykrishnan (Vijaykrishnan Narayanan) [3] [4] [5] [8]

Colors in the list of coauthors

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)