| |
| 2008 | ||
|---|---|---|
| 5 | EE | Sebastian Kinder, Rolf Drechsler: Modeling and proving functional completeness in formal verification of counting heads. STTT 10(6): 521-534 (2008) |
| 2007 | ||
| 4 | EE | Sebastian Kinder, Rolf Drechsler: Proving Completeness of Properties in Formal Verification of Counting Heads for Railways. DSD 2007: 396-403 |
| 2006 | ||
| 3 | EE | Rolf Drechsler, Görschwin Fey, Sebastian Kinder: An Integrated Approach for Combining BDD and SAT Provers. VLSI Design 2006: 237-242 |
| 2005 | ||
| 2 | EE | Sebastian Kinder, Görschwin Fey, Rolf Drechsler: Controlling the Memory During Manipulation of Word-Level Decision Diagrams. ISMVL 2005: 250-255 |
| 2003 | ||
| 1 | EE | Görschwin Fey, Sebastian Kinder, Rolf Drechsler: Using Games for Benchmarking and Representing the Complete Solution Space using Symbolic Techniques. ISMVL 2003: 361-366 |
| 1 | Rolf Drechsler | [1] [2] [3] [4] [5] |
| 2 | Görschwin Fey | [1] [2] [3] |