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Qiuyang Wu

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2006
2EEK. A. Rajagopal, R. Sivakumar, N. V. Arvind, C. Sreeram, Vish Visvanathan, Shailendra Dhuri, Roopesh Chander, Patrick Fortner, Subra Sripada, Qiuyang Wu: A Comprehensive Solution for True Hierarchical Timing and Crosstalk Delay Signoff. VLSI Design 2006: 277-282
2002
1EEAjay J. Daga, Loa Mize, Subramanyam Sripada, Chris Wolff, Qiuyang Wu: Automated timing model generation. DAC 2002: 146-151

Coauthor Index

1N. V. Arvind [2]
2Roopesh Chander [2]
3Ajay J. Daga [1]
4Shailendra Dhuri [2]
5Patrick Fortner [2]
6Loa Mize [1]
7K. A. Rajagopal [2]
8R. Sivakumar [2]
9C. Sreeram [2]
10Subra Sripada [2]
11Subramanyam Sripada [1]
12Vish Visvanathan [2]
13Chris Wolff [1]

Colors in the list of coauthors

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)