Rama Sangireddy

2009
20	EE	Hui Wang, Rama Sangireddy, Sandeep Baldawa: Optimizing Instruction Scheduling through Combined In-Order and O-O-O Execution in SMT Processors. IEEE Trans. Parallel Distrib. Syst. 20(3): 389-403 (2009)
2008
19	EE	Terrell Bennett, Rama Sangireddy: An Optimal Multi-Functional Unit Dynamic Instruction Selection Logic at Submicron Technologies. VLSI Design 2008: 267-272
18	EE	Hui Wang, Sandeep Baldawa, Rama Sangireddy: Dynamic Error Detection for Dependable Cache Coherency in Multicore Architectures. VLSI Design 2008: 279-285
17	EE	Rama Sangireddy, Jatan P. Shah: Operand-Load-Based Split Pipeline Architecture for High Clock Rate and Commensurable IPC. IEEE Trans. Parallel Distrib. Syst. 19(4): 529-544 (2008)
16	EE	Hui Wang, Rama Sangireddy: Streamlining long latency instructions for seamlessly combined out-of-order and in-order execution. Microprocessors and Microsystems - Embedded Hardware Design 32(7): 375-385 (2008)
2007
15	EE	Jatan P. Shah, Rama Sangireddy: Higher Clock Rate at Comparable IPC Through Reduced Circuit Complexity in Instruction Format Based Pipeline Clustering. ISCAS 2007: 4012-4015
14		Rama Sangireddy, Prabhu Rajamani: Scalable Reconfigurable Architectures for High-Performance Energy-Efficient Multimedia Processing. I. J. Comput. Appl. 14(2): 68-78 (2007)
13	EE	Rama Sangireddy: Register port complexity reduction in wide-issue processors with selective instruction execution. Microprocessors and Microsystems 31(1): 51-62 (2007)
2006
12	EE	Prabhu Rajamani, Jatan P. Shah, Vadhiraj Sankaranarayanan, Rama Sangireddy: High performance and alleviated hot-spot problem in processor frontend with enhanced instruction fetch bandwidth utilization. IPCCC 2006
11	EE	Rama Sangireddy: Fast and low-power processor front-end with reduced rename logic circuit complexity. ISCAS 2006
10	EE	Rama Sangireddy: Instruction Format Based Selective Execution for Register Port Complexity Reduction in High-Performance Processors. ITNG 2006: 227-232
9	EE	Rama Sangireddy, Prabhu Rajamani, Shwetha Gaddam: Performance Optimization with Scalable Reconfigurable Computing Systems. VLSI Design 2006: 381-386
8	EE	Rama Sangireddy: Reducing Rename Logic Complexity for High-Speed and Low-Power Front-End Architectures. IEEE Trans. Computers 55(6): 672-685 (2006)
2005
7	EE	Rama Sangireddy, Natsuhiko Futamura, Srinivas Aluru, Arun K. Somani: Scalable, memory efficient, high-speed IP lookup algorithms. IEEE/ACM Trans. Netw. 13(4): 802-812 (2005)
2004
6	EE	Rama Sangireddy: Register Organization for Enhanced On-Chip Parallelism. ASAP 2004: 180-190
5	EE	Rama Sangireddy, Arun K. Somani: Exploiting Quiescent States in Register Lifetime. ICCD 2004: 368-374
4	EE	Rama Sangireddy, Huesung Kim, Arun K. Somani: Low-Power High-Performance Reconfigurable Computing Cache Architectures. IEEE Trans. Computers 53(10): 1274-1290 (2004)
2003
3	EE	Rama Sangireddy, Arun K. Somani: Application-Specific Computing with Adaptive Register File Architectures. ASAP 2003: 183-
2	EE	Rama Sangireddy, Huesung Kim, Arun K. Somani: Timing Issues of Operating Mode Switch in High Performance Reconfigurable Architectures. HiPC 2003: 23-33
2002
1	EE	Rama Sangireddy, Huesung Kim, Arun K. Somani: Low-Power High-Performance Adaptive Computing Architectures for Multimedia Processing. HiPC 2002: 124-136

Coauthor Index

1	Srinivas Aluru	[7]
2	Sandeep Baldawa	[18] [20]
3	Terrell Bennett	[19]
4	Natsuhiko Futamura	[7]
5	Shwetha Gaddam	[9]
6	Huesung Kim	[1] [2] [4]
7	Prabhu Rajamani	[9] [12] [14]
8	Vadhiraj Sankaranarayanan	[12]
9	Jatan P. Shah	[12] [15] [17]
10	Arun K. Somani	[1] [2] [3] [4] [5] [7]
11	Hui Wang	[16] [18] [20]

Colors in the list of coauthors