| 2008 |
|---|
| 4 | EE | S. Biswas,
S. Mukhopadhyay,
A. Patra,
D. Sarkar:
Unified Technique for on-Line Testing of Digital Circuits: Delay and Stuck-at Fault Models.
Journal of Circuits, Systems, and Computers 17(6): 1069-1089 (2008) |
| 2006 |
|---|
| 3 | EE | Prabir K. Saha,
Ashudeb Dutta,
A. Patra,
T. K. Bhattacharyya:
Design of a 1 V Low Power 900 MHz QVCO.
VLSI Design 2006: 57-62 |
| 2005 |
|---|
| 2 | EE | S. Biswas,
P. Srikanth,
R. Jha,
S. Mukhopadhyay,
A. Patra,
D. Sarkar:
On-Line Testing of Digital Circuits for n-Detect and Bridging Fault Models.
Asian Test Symposium 2005: 88-93 |
| 1 | EE | P. Gupta,
A. Patra:
Super-stable energy based switching control scheme for DC-DC buck converter circuits.
ISCAS (4) 2005: 3063-3066 |
