Zoran A. Salcic

2007
28	EE	Kevin I-Kai Wang, Waleed H. Abdulla, Zoran A. Salcic: Multi-agent System with Hybrid Intelligence Using Neural Network and Fuzzy Inference Techniques. IEA/AIE 2007: 473-482
27	EE	Ivan Radojevic, Zoran A. Salcic, Partha S. Roop: McCharts and Multiclock FSMs for modeling large scale systems. MEMOCODE 2007: 3-12
26	EE	Kevin I-Kai Wang, Waleed H. Abdulla, Zoran A. Salcic: Multi-agent Software Control System with Hybrid Intelligence for Ubiquitous Intelligent Environments. UIC 2007: 1046-1055
2006
25	EE	Flavius Gruian, Partha S. Roop, Zoran A. Salcic, Ivan Radojevic: The SystemJ approach to system-level design. MEMOCODE 2006: 149-158
24	EE	Roshan Duraisamy, Zoran A. Salcic, Miguel Morales-Sandoval, Claudia Feregrino Uribe: A Fast Elliptic Curve Based Key Agreement Protocol-on-Chip (PoC) for Securing Networked Embedded Systems. RTCSA 2006: 154-161
23	EE	Zoran A. Salcic, Flavius Gruian, Partha S. Roop, Alif Wahid: A Scheduler Support Unit for Reactive Microprocessors. RTCSA 2006: 368-372
22	EE	Kevin I-Kai Wang, Waleed H. Abdulla, Zoran A. Salcic: Distributed Embedded Intelligence Room with Multi-agent Cooperative Learning. UIC 2006: 147-156
21	EE	Ivan Radojevic, Zoran A. Salcic, Partha S. Roop: Design of Heterogeneous Embedded Systems Using DFCharts Model of Computation. VLSI Design 2006: 461-464
20	EE	Ivan Radojevic, Zoran A. Salcic, Partha S. Roop: Modeling Embedded Systems: From SystemC and Esterel to DFCharts. IEEE Design & Test of Computers 23(5): 348-358 (2006)
19	EE	Zoran A. Salcic, Dong Hui, Partha S. Roop, Morteza Biglari-Abhari: HiDRA - A reactive multiprocessor architecture for heterogeneous embedded systems. Microprocessors and Microsystems 30(2): 72-85 (2006)
2005
18		Laurence Tianruo Yang, Hamid R. Arabnia, Jürgen Becker, Masaharu Imai, Zoran A. Salcic: Proceedings of The 2005 International Conference on Embedded Systems and Applications, ESA 2005, Las Vegas, Nevada, USA, June 27-30, 2005 CSREA Press 2005
17	EE	Zoran A. Salcic, Dong Hui, Partha S. Roop, Morteza Biglari-Abhari: REMIC: design of a reactive embedded microprocessor core. ASP-DAC 2005: 977-981
16	EE	Lei Yang, Morteza Biglari-Abhari, Zoran A. Salcic: A Power-Efficient Processor Core for Reactive Embedded Applications. Asia-Pacific Computer Systems Architecture Conference 2005: 131-142
15	EE	Flavius Gruian, Zoran A. Salcic: Designing a Concurrent Hardware Garbage Collector for Small Embedded Systems. Asia-Pacific Computer Systems Architecture Conference 2005: 281-294
14	EE	Ivan Radojevic, Zoran A. Salcic, Partha S. Roop: Modelling Heterogeneous Embedded Systems in DFCarts. FDL 2005: 441-453
13	EE	Ivan Radojevic, Zoran A. Salcic, Partha S. Roop: A New Model for Heterogeneous Embedded Systems - What Esterel and SyncCharts Need to Become a Suitable Specification Platform. International Journal of Software Engineering and Knowledge Engineering 15(2): 405-410 (2005)
2004
12	EE	Partha S. Roop, Zoran A. Salcic, M. W. Sajeewa Dayaratne: Towards direct execution of esterel programs on reactive processors. EMSOFT 2004: 240-248
11		Zoran A. Salcic, Partha S. Roop: Customizing Processor Cores to Support Reactivity. ERSA 2004: 194-202
10		Zoran A. Salcic, Partha S. Roop, Dong Hui, Ivan Radojevic: HiDRA: A New Architecture for Heterogeneous Embedded Systems. ESA/VLSI 2004: 164-170
9	EE	Zoran A. Salcic, Partha S. Roop, Morteza Biglari-Abhari, Abbas Bigdeli: REFLIX: a processor core with native support for control-dominated embedded applications. Microprocessors and Microsystems 28(1): 13-25 (2004)
2003
8	EE	Partha S. Roop, Zoran A. Salcic, Morteza Biglari-Abhari, Abbas Bigdeli: A New Reactive Processor with Architectural Support for Control Dominated Embedded Systems. VLSI Design 2003: 189-194
2002
7	EE	Zoran A. Salcic, Partha S. Roop, Morteza Biglari-Abhari, Abbas Bigdeli: REFLIX: A Processor Core for Reactive Embedded Applications. FPL 2002: 945-945
2001
6		Zoran A. Salcic: High-speed customizable fuzzy-logic processor: architecture and implementation. IEEE Transactions on Systems, Man, and Cybernetics, Part A 31(6): 731-737 (2001)
5	EE	Jayanthi Sivaswamy, Zoran A. Salcic, K. L. Ling: A Real-Time Implementation of Nonlinear Unsharp Masking with FPLDs. Real-Time Imaging 7(2): 195-202 (2001)
1999
4		R. Bruce Maunder, Zoran A. Salcic, George G. Coghill: High-Level Hierachical HDL Synthesis of Pipelined FPGA-Based Circuits Using Synchronous Modules. FPL 1999: 377-384
3	EE	Zoran A. Salcic, Jayanthi Sivaswamy: IMECO: A Reconfigurable FPGA-based Image Enhancement Co-Processor Framework. Real-Time Imaging 5(6): 385-395 (1999)
1997
2		R. Bruce Maunder, Zoran A. Salcic, George G. Coghill: FPLD HDL synthesis employing high-level evolutionary algorithm optimisation. FPL 1997: 265-273
1996
1		Zoran A. Salcic, R. Bruce Maunder: CCSimP - An Instruction-level Custom-Configurable Processor for FPLDs. FPL 1996: 280-289

Coauthor Index

1	Waleed H. Abdulla	[22] [26] [28]
2	Hamid R. Arabnia	[18]
3	Jürgen Becker	[18]
4	Abbas Bigdeli	[7] [8] [9]
5	Morteza Biglari-Abhari	[7] [8] [9] [16] [17] [19]
6	George G. Coghill	[2] [4]
7	M. W. Sajeewa Dayaratne	[12]
8	Roshan Duraisamy	[24]
9	Flavius Gruian	[15] [23] [25]
10	Dong Hui	[10] [17] [19]
11	Masaharu Imai	[18]
12	K. L. Ling	[5]
13	R. Bruce Maunder	[1] [2] [4]
14	Miguel Morales-Sandoval	[24]
15	Ivan Radojevic	[10] [13] [14] [20] [21] [25] [27]
16	Partha S. Roop	[7] [8] [9] [10] [11] [12] [13] [14] [17] [19] [20] [21] [23] [25] [27]
17	Jayanthi Sivaswamy	[3] [5]
18	Claudia Feregrino Uribe (Claudia Feregrino)	[24]
19	Alif Wahid	[23]
20	Kevin I-Kai Wang	[22] [26] [28]
21	Laurence Tianruo Yang	[18]
22	Lei Yang	[16]

Colors in the list of coauthors