| 2006 |
|---|
| 7 | EE | Vivek Garg,
Vikram Chandrasekhar,
Milagros Sashikánth,
V. Kamakoti:
An Area and Configuration-Bit Optimized CLB Architecture and Timing-Driven Packing for FPGAs.
VLSI Design 2006: 507-510 |
| 2005 |
|---|
| 6 | EE | E. Syam Sundar Reddy,
Vikram Chandrasekhar,
Milagros Sashikánth,
V. Kamakoti,
Narayanan Vijaykrishnan:
Cluster-based detection of SEU-caused errors in LUTs of SRAM-based FPGAs.
ASP-DAC 2005: 1200-1203 |
| 5 | EE | Vivek Garg,
Vikram Chandrasekhar,
Milagros Sashikánth,
V. Kamakoti:
A novel CLB architecture and circuit packing algorithm for logic-area reduction in SRAM-based FPGAs.
ASP-DAC 2005: 791-794 |
| 4 | EE | Vivek Garg,
Vikram Chandrasekhar,
Milagros Sashikánth,
V. Kamakoti:
A function generator-based reconfigurable system.
ASP-DAC 2005: 905-909 |
| 3 | EE | E. Syam Sundar Reddy,
Vikram Chandrasekhar,
Milagros Sashikánth,
V. Kamakoti,
Narayanan Vijaykrishnan:
Efficient methodology for detection and correction of SEU-based interconnect errors in FPGAs using partial reconfiguration (abstract only).
FPGA 2005: 265 |
| 2 | EE | E. Syam Sundar Reddy,
Vikram Chandrasekhar,
Milagros Sashikánth,
V. Kamakoti,
Narayanan Vijaykrishnan:
Online Detection and Diagnosis of Multiple Configuration Upsets in LUTs of SRAM-Based FPGAs.
IPDPS 2005 |
| 1 | EE | E. Syam Sundar Reddy,
Vikram Chandrasekhar,
Milagros Sashikánth,
V. Kamakoti,
Narayanan Vijaykrishnan:
Detecting SEU-Caused Routing Errors in SRAM-Based FPGAs.
VLSI Design 2005: 736-741 |
