| 2006 |
|---|
| 5 | EE | Jayashree Sridharan,
Tom Chen:
Modeling multiple input switching of CMOS gates in DSM technology using HDMR.
DATE 2006: 626-631 |
| 4 | EE | Jayashree Sridharan,
Tom Chen:
Gate Delay Modeling with Multiple Input Switching for Static (Statistical) Timing Analysis.
VLSI Design 2006: 323-328 |
| 2005 |
|---|
| 3 | EE | Sameer Shivle,
Prasanna Sugavanam,
Howard Jay Siegel,
Anthony A. Maciejewski,
Tarun Banka,
Kiran Chindam,
Steve Dussinger,
Andrew Kutruff,
Prashanth Penumarthy,
Prakash Pichumani,
Praveen Satyasekaran,
David Sendek,
Jay Smith,
J. Sousa,
Jayashree Sridharan,
Jose Velazco:
Mapping subtasks with multiple versions on an ad hoc grid.
Parallel Computing 31(7): 671-690 (2005) |
| 2004 |
|---|
| 2 | EE | Sameer Shivle,
Ralph H. Castain,
Howard Jay Siegel,
Anthony A. Maciejewski,
Tarun Banka,
Kiran Chindam,
Steve Dussinger,
Prakash Pichumani,
Praveen Satyasekaran,
William W. Saylor,
David Sendek,
J. Sousa,
Jayashree Sridharan,
Prasanna Sugavanam,
Jose Velazco:
Static Mapping of Subtasks in a Heterogeneous Ad Hoc Grid Environment.
IPDPS 2004 |
| 1 | EE | Sameer Shivle,
Howard Jay Siegel,
Anthony A. Maciejewski,
Tarun Banka,
Kiran Chindam,
Steve Dussinger,
Andrew Kutruff,
Prashanth Penumarthy,
Prakash Pichumani,
Praveen Satyasekaran,
David Sendek,
J. Sousa,
Jayashree Sridharan,
Prasanna Sugavanam,
Jose Velazco:
Mapping of Subtasks with Multiple Versions in a Heterogeneous Ad Hoc Grid Environment.
ISPDC/HeteroPar 2004: 380-387 |
