| 2008 |
|---|
| 27 | | Abdel Ejnioui,
Paul Bao:
A Parallel Array to Accelerate GFA Modeling in Video Coding.
ERSA 2008: 252-258 |
| 2007 |
|---|
| 26 | | Abdel Ejnioui,
Paul Bao:
Hardware Acceleration of the Generalized Finite Automata Algorithm.
CDES 2007: 140-146 |
| 25 | | Abdel Ejnioui:
Prototyping of a Two-Phase Micropipeline on FPGAs.
ERSA 2007: 138-146 |
| 24 | EE | Abdel Ejnioui:
FPGA Prototyping of a Two-Phase Self-Oscillating Micropipeline.
ISVLSI 2007: 437-438 |
| 23 | EE | Ronald F. DeMara,
Yili Tseng,
Abdel Ejnioui:
Tiered Algorithm for Distributed Process Quiescence and Termination Detection.
IEEE Trans. Parallel Distrib. Syst. 18(11): 1529-1538 (2007) |
| 2006 |
|---|
| 22 | EE | Anuja Jayraj Thakkar,
Abdel Ejnioui:
Pipelining of double precision floating point division and square root operations.
ACM Southeast Regional Conference 2006: 488-493 |
| 21 | | Heng Tan,
Ronald F. DeMara,
Anuja Jayraj Thakkar,
Abdel Ejnioui,
Jason Sattler:
Complexity and Performance Evaluation of Two Partial Reconfiguration Interfaces on FPGAs: A Case Study.
ERSA 2006: 253-256 |
| 20 | EE | Rashad Oreifej,
Abdelhalim Alsharqawi,
Abdel Ejnioui:
Synthesis of Pipelined SRSL Circuits.
ISVLSI 2006: 71-76 |
| 19 | EE | Abdelhalim Alsharqawi,
Abdel Ejnioui:
Clockless Pipelining for Coarse Grain Datapaths.
VLSI Design 2006: 749-753 |
| 2005 |
|---|
| 18 | | Abdel Ejnioui,
Ronald F. DeMara:
Area Reclamation Strategies and Metrics for SRAM-Based Reconfigurable Devices.
ERSA 2005: 196-202 |
| 17 | EE | Abdelhalim Alsharqawi,
Abdel Ejnioui:
Synthesis of Self-Resetting Stage Logic Pipelines.
ISVLSI 2005: 260-262 |
| 2004 |
|---|
| 16 | EE | Abdel Ejnioui,
Abdelhalim Alsharqawi:
Self-resetting stage logic pipelines.
ACM Great Lakes Symposium on VLSI 2004: 174-177 |
| 15 | EE | Abdel Ejnioui,
Abdelhalim Alsharqawi:
Pipeline-Level Control of Self-Resetting Pipelines.
DSD 2004: 342-349 |
| 14 | EE | Ravi Namballa,
Nagarajan Ranganathan,
Abdel Ejnioui:
Control and Data Flow Graph Extraction for High-Level Synthesis.
ISVLSI 2004: 192 |
| 13 | EE | Abdel Ejnioui,
Abdelhalim Alsharqawi:
Pipeline Design Based on Self-Resetting Stage Logic.
ISVLSI 2004: 254-257 |
| 12 | EE | Abdel Ejnioui,
Abdelkader Rhiati:
A Reconfigurable Memory Management Core for Java Applications.
ISVLSI 2004: 309-312 |
| 2003 |
|---|
| 11 | EE | W. Kuang,
J. S. Yuan,
Abdel Ejnioui:
Supply Voltage Scalable System Design Using Self-Timed Circuits.
ISVLSI 2003: 161-166 |
| 10 | EE | Abdel Ejnioui,
N. Ranganathan:
Multiterminal net routing for partial crossbar-based multi-FPGA systems.
IEEE Trans. VLSI Syst. 11(1): 71-78 (2003) |
| 9 | EE | Abdel Ejnioui,
N. Ranganathan:
Routing on field-programmable switch matrices.
IEEE Trans. VLSI Syst. 11(2): 283-287 (2003) |
| 2002 |
|---|
| 8 | EE | K. Sitaraman,
N. Ranganathan,
Abdel Ejnioui:
A VLSI Architecture for Object Recognition Using Tree Matching.
ASAP 2002: 325-334 |
| 2001 |
|---|
| 7 | EE | Abdel Ejnioui,
N. Ranganathan:
A partitioning algorithm for technoiogy-mapped designs on single-chip emulation systems.
IEEE Trans. VLSI Syst. 9(2): 407-410 (2001) |
| 2000 |
|---|
| 6 | EE | Abdel Ejnioui,
N. Ranganathan:
Design Partitioning on Single-Chip Emulation Systems.
VLSI Design 2000: 234-239 |
| 5 | EE | Abdel Ejnioui,
N. Ranganathan:
Routing on Switch Matrix Multi-FPGA Systems.
VLSI Design 2000: 248-253 |
| 1999 |
|---|
| 4 | EE | Abdel Ejnioui,
N. Ranganathan:
Multi-Terminal Net Routing for Partial Crossbar-Based Multi-FPGA Systems.
FPGA 1999: 176-185 |
| 3 | EE | Vamsi Krishna,
N. Ranganathan,
Abdel Ejnioui:
A tree-matching chip.
IEEE Trans. VLSI Syst. 7(2): 277-280 (1999) |
| 1996 |
|---|
| 2 | EE | Vamsi Krishna,
Abdel Ejnioui,
N. Ranganathan:
A tree matching chip.
VLSI Design 1996: 280-285 |
| 1995 |
|---|
| 1 | EE | Abdel Ejnioui,
N. Ranganathan:
Systolic algorithms for tree pattern matching.
ICCD 1995: 650-702 |
