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| 2008 | ||
|---|---|---|
| 4 | EE | Aman Kokrady, C. P. Ravikumar, Nitin Chandrachoodan: Memory Yield Improvement through Multiple Test Sequences and Application-Aware Fault Models. VLSI Design 2008: 169-174 |
| 2006 | ||
| 3 | EE | Aman Kokrady, Theo J. Powell, S. Ramakrishnan: Reducing Design Verification Cycle Time through Testbench Redundancy. VLSI Design 2006: 243-248 |
| 2004 | ||
| 2 | EE | Aman Kokrady, C. P. Ravikumar: Fast, Layout-Aware Validation of Test-Vectors for Nanometer-Related Timing Failures. VLSI Design 2004: 597- |
| 2003 | ||
| 1 | EE | Aman Kokrady, C. P. Ravikumar: Static Verification of Test Vectors for IR Drop Failure. ICCAD 2003: 760-764 |
| 1 | Nitin Chandrachoodan | [4] |
| 2 | Theo J. Powell | [3] |
| 3 | S. Ramakrishnan | [3] |
| 4 | C. P. Ravikumar | [1] [2] [4] |