| 2006 |
|---|
| 6 | EE | Subodh M. Reddy,
Gustavo R. Wilke,
Rajeev Murgai:
Analyzing timing uncertainty in mesh-based clock architectures.
DATE 2006: 1097-1102 |
| 5 | EE | Chao-Yang Yeh,
Gustavo R. Wilke,
Hongyu Chen,
Subodh M. Reddy,
Hoa-van Nguyen,
Takashi Miyoshi,
William W. Walker,
Rajeev Murgai:
Clock Distribution Architectures: A Comparative Study.
ISQED 2006: 85-91 |
| 4 | EE | Subodh M. Reddy,
Rajeev Murgai:
Accurate Substrate Noise Analysis Based on Library Module Characterization.
VLSI Design 2006: 355-362 |
| 2005 |
|---|
| 3 | | Hongyu Chen,
Chao-Yang Yeh,
Gustavo R. Wilke,
Subodh M. Reddy,
Hoa-van Nguyen,
William W. Walker,
Rajeev Murgai:
A sliding window scheme for accurate clock mesh analysis.
ICCAD 2005: 939-946 |
| 2004 |
|---|
| 2 | EE | Rajeev Murgai,
Subodh M. Reddy,
Takashi Miyoshi,
Takeshi Horie,
Mehdi Baradaran Tahoori:
Sensitivity-Based Modeling and Methodology for Full-Chip Substrate Noise Analysis.
DATE 2004: 610-615 |
| 1995 |
|---|
| 1 | | Subodh M. Reddy,
Wolfgang Kunz,
Dhiraj K. Pradhan:
Novel Verification Framework Combining Structural and OBDD Methods in a Synthesis Environment.
DAC 1995: 414-419 |
