| 2006 |
|---|
| 3 | EE | Kavish Seth,
K. N. Viswajith,
S. Srinivasan,
V. Kamakoti:
Ultra Folded High-Speed Architectures for Reed-Solomon Decoders.
VLSI Design 2006: 517-520 |
| 2004 |
|---|
| 2 | EE | Kavish Seth,
P. Rangarajan,
S. Srinivasan,
V. Kamakoti,
V. Bala Kuteshwar:
A Parallel Architectural Implementation Of The New Three-Step Search Algorithm For Block Motion Estimation.
VLSI Design 2004: 1071-1076 |
| 2002 |
|---|
| 1 | EE | Kavish Seth,
S. Srinivasan:
VLSI Implementation of 2-D DWT/IDWT Cores Using 9/7-Tap Filter Banks Based on the Non-Expansive Symmetric Extension Scheme.
VLSI Design 2002: 435-440 |
